Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures over a first semiconductor fin and multiple second semiconductor nanostructures over a second semiconductor fin. A topmost second semiconductor nanostructure of the second semiconductor nanostructures is thinner than one or more of lower semiconductor nanostructures of the second semiconductor nanostructures. The semiconductor device structure also includes a first metal gate stack wrapped around the first semiconductor nanostructures. The semiconductor device structure further includes a second metal gate stack wrapped around the second semiconductor nano structures.

Abstract: A spring configured to be fixed to a housing and nested within a dial that is rotatable about the spring. The dial has a plurality of spaced apart inwardly facing teeth that are adjacent the spring. The spring is configured to facilitate rotation of the dial about the spring. The spring includes a central body having at least one anchor configured to connect the spring to the housing. The spring also includes at least one arm having a first end connected to the central body. The spring also includes a second end of the arm that is connected to a bulb. The bulb can be enclosed and include an exterior surface with a node that is on distal from the central body. The node is sized to fit in a space between adjacent teeth. The enclosed bulb biases the node toward the spaces between the teeth.

Abstract: A semiconductor device includes a substrate, two source/drain (S/D) regions over the substrate, a channel region between the two S/D regions and including a semiconductor material, a deposited capacitor material (DCM) layer over the channel region a dielectric layer over the DCM layer and a metallic gate electrode layer over the dielectric layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: A device includes a semiconductor substrate, a source feature and a drain feature over the semiconductor substrate, a stack of semiconductor layers interposed between the source feature and the drain feature, a gate portion, and an inner spacer of a dielectric material. The gate portion is between two vertically adjacent layers of the stack of semiconductor layers and between the source feature and the drain feature. Moreover, the gate portion has a first sidewall surface and a second sidewall surface opposing the first sidewall surface. The inner spacer is on the first sidewall surface and between the gate portion and the drain feature. The second sidewall surface is in direct contact with the source feature.

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The gate stack is partially embedded in the first nanostructure. The semiconductor device structure includes a first source/drain layer surrounding the first nanostructure and adjacent to the gate stack. The semiconductor device structure includes a contact structure surrounding the first source/drain layer. A first portion of the contact structure is between the first source/drain layer and the substrate.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.

Abstract: An oil filter wrench having a base, a main gear, a plurality of claws each having a gear portion and an arm configured to engage an oil filter. The gear portions are rotatably disposed within the base and configured to engage the main gear such that when the main gear rotates; the arms correspondingly extend or contract relative to the base. The oil filter wrench also includes a main spring. The main spring is disposed within a cavity defined by the main gear. The main spring is configured to selectively bias the main gear toward rotation in either a first direction or a second direction opposite to the first direction. The oil filter wrench is characterised in that it also includes a switching mechanism a switching mechanism. The switching mechanism is configured to selectively toggle between a first position and a second position. In the first position, the switching mechanism engages a first tine of the main spring such that the main gear is biased to rotate in the first direction.

Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.

Abstract: A power conversion system with ripple injection includes an AC-DC conversion unit, a voltage regulation unit, at least one DC-DC conversion unit, at least one load, and a first control unit. The voltage regulation unit provides a DC link and receives one portion of an input power as an energy storage power. Each DC-DC conversion unit receives the other portion of the input power as an output power. The at least one load correspondingly receives the output power for being supplied power. The first control unit is coupled to the DC link, the at least one DC-DC conversion unit, and the at least one load. The first control unit controls the at least one DC-DC conversion unit to adjust a magnitude of a ripple of the output power to perform a ripple injection operation according to a magnitude of a ripple of the input power.

Abstract: Techniques and examples of efficient detection of a transmission session in New Radio unlicensed spectrum (NR-U) are described. An apparatus (e.g., user equipment (UE)) detects presence of an indication from a base station of a wireless network in an NR-U. The apparatus determines that a transmission opportunity (TXOP) follows the indication responsive to the detecting. The apparatus then receives a downlink (DL) transmission in the NR-U from the base station during the TXOP.

Abstract: An electronic device and a manufacturing method thereof are provided. The method includes at least the following steps. An insulating encapsulant is formed to encapsulate a multi-layered structure and a semiconductor die, where the multi-layered structure includes a first conductor, a diffusion barrier layer on the first conductor, and a metallic layer on the diffusion barrier layer, and the insulating encapsulant at least exposes a portion of the semiconductor die and a portion of the first conductor. A redistribution structure is formed over the insulating encapsulant, the semiconductor die, and the first conductor. The metallic layer is removed to form a recess in the insulating encapsulant. A second conductor is formed in the recess over the diffusion barrier layer, where the first conductor, the diffusion barrier layer, and the second conductor form a conductive structure that is electrically coupled to the semiconductor die through the redistribution structure.

Abstract: An anti-virus chip includes a first connection terminal, a second connection terminal, a detection unit and a processing unit. The first connection terminal and the second connection terminal are respectively coupled to a connection port and a system circuit of an electronic device. The detection unit detects whether the connection port is connected to an external device via the first connection terminal. When the detection unit detects that the connection port is connected to the external device, the processing unit performs a virus-scan program on the external device to determine whether a virus exists in the external device. When determining that a virus does not exist in the external device, the processing unit establishes a first transmission path between the first connection terminal and the second connection terminal. When determining that a virus exists in the external device, the processing unit does not establish the first transmission path.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor fin structure over a substrate, forming a dielectric fin structure laterally spaced apart from the semiconductor fin structure, forming a source/drain spacer between the semiconductor fin structure and the dielectric fin structure, etching an upper portion of the semiconductor fin structure to expose a lower portion of the semiconductor fin structure, and forming a source/drain feature over the lower portion of the semiconductor fin structure. The source/drain spacer is interposed between the source/drain feature and the dielectric fin structure.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: Backside interconnect structures having reduced critical dimensions for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure over a front-side of a substrate; a first backside interconnect structure over a backside of the substrate, the first backside interconnect structure including first conductive features having tapered sidewalls with widths that narrow in a direction away from the substrate; a power rail extending through the substrate, the power rail being electrically coupled to the first conductive features; and a first source/drain contact extending from the power rail to a first source/drain region of the first transistor structure.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.