Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

Abstract: The invention relates to a photodiode, like an photovoltaic (OPV) cell or photodetector (OPD), comprising, between the photoactive layer and an electrode, a hole selective layer (HSL) for modifying the work function of the electrode and/or the photoactive layer, wherein the HSL comprises a fluoropolymer and optionally a conductive polymer, and to a composition comprising such a fluoropolymer and a conductive polymer.

Abstract: A finFET device that includes a substrate and at least one semiconductor fin extending from the substrate. The fin may include a plurality of wide portions comprising a first semiconductor material and one or more narrow portions. The one or more narrow portions have a second width less than the first width of the wide portions. Each of the one or more narrow portions separates two of the plurality of wide portions from one another such that the plurality of wide portions and the one or more narrow portions are arranged alternatingly in a substantially vertical direction that is substantially perpendicular with a surface of the substrate. The fin may also include a channel layer covering sidewalls of the plurality of wide portions and a sidewall of the one or more narrow portions.

Abstract: A yellow light emitting device may have a light source and a color converter wherein at most 1% of the total emitted radiant power of the yellow light emitting device is emitted in a wavelength range shorter than 520 nm, as well as the use of the yellow light emitting device.

Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first channel structure, a first gate dielectric layer surrounding the first channel structure, and a first metal gate surrounding first gate dielectric layer. The first metal gate includes a first metal layer in direct contact with the first gate dielectric layer and a first metal cap in direct contact with the first gate dielectric layer, wherein the first metal cap is in direct contact with the first metal layer.

Abstract: A semiconductor structure includes an active layer, a first gate insulator layer disposed over the active layer, a first gate layer disposed over the gate insulator layer, at least one charged layer disposed between the first gate insulator layer and the active layer, and a pair of contact structures disposed over the active layer. The at least one charged layer includes an oxide material.

Abstract: A keyboard includes a plurality of keyswitches, a plastic baseplate, and a membrane circuit board. Each keyswitch has a keycap, a lifting mechanism and an elastic member. The lifting mechanism is movably connected to the keycap. The elastic member abuts against the keycap. The plastic baseplate has a first hole formed corresponding to each elastic member and has a connecting structure corresponding to each lifting mechanism. The connecting structure is movably connected to the lifting mechanism to make the keycap movable relative to the plastic baseplate. The membrane circuit board is disposed under the plastic baseplate. Each elastic member passes through the first hole on the plastic baseplate to be disposed on the membrane circuit board. When the keycap is pressed, the elastic member deforms downward to trigger the membrane circuit board. When the keycap is released, the elastic member returns the keycap to its original position.

Abstract: A keyboard is applied to mounting on a holding baseplate of a computer device and includes a plurality of keyswitches, a membrane circuit board and a baseplate. The membrane circuit board is disposed under the plurality of keyswitches. The baseplate is disposed between the plurality of keyswitches and the membrane circuit board and is connected to the plurality of keyswitches, so as to make the plurality of keyswitches movable relative to the baseplate for triggering the membrane circuit board. The baseplate has a plurality of hooks. The plurality of hooks passes through the membrane circuit board to be engaged with a plurality of engaging hole structures of the holding baseplate respectively, so as to detachably mount the keyboard on the computer device. A number of the plurality of hooks is greater than forty.

Abstract: A backlight module is applied to providing light to a plurality of keyswitches of a keyboard. Each keyswitch has a keycap and an elastic member abutting against the keycap. The backlight module includes a membrane circuit board and a light guide plate. The membrane circuit board has a light emitting diode corresponding to the keyswitch. The light emitting diode is located at a side of the elastic member and emits light to the keycap. The light guide plate is disposed on the membrane circuit board. The light guide plate has a slot hole for containing the light emitting diode and has a hole corresponding to the elastic member. An optical microstructure is formed on the light guide plate for guiding light of the light emitting diode to be incident to the keycap. The elastic member passes through the hole to be disposed on the membrane circuit board.

Abstract: Various solutions for Ultra-Reliable Low-Latency Communication (URLLC) enhancement on unlicensed spectrum in mobile communications are described. An apparatus, implementable in a UE, obtains a UE-initiated channel occupancy time (COT). The apparatus then performs an uplink (UL) transmission to a network during the UE-initiated COT.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base. The semiconductor device structure includes a first multilayer stack over the base. The first multilayer stack includes a first channel layer and a second channel layer over and spaced apart from the first channel layer. The semiconductor device structure includes a gate stack over the substrate. The gate stack wraps around the first multilayer stack. The semiconductor device structure includes an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the base. The semiconductor device structure includes a bottom spacer over the base. The semiconductor device structure includes a first source/drain structure over the bottom spacer and connected to the second channel layer.

Abstract: A method of making a semiconductor device includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.

Abstract: A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: A method includes fabricating a first-type active-region semiconductor, depositing a layer of dielectric material covering the first-type active-region semiconductor structure, and fabricating a second-type active-region semiconductor structure atop the layer of dielectric material. The method includes forming a front-side power rail and a front-side signal line extending in the first direction in a front-side metal layer overlying a first insulating material that covers the first-type active-region semiconductor. The front-side power rail is conductively connected to a second source conductive segment intersecting the second-type active-region semiconductor structure. The method includes forming a back-side metal layer on a backside of the substrate, and forming a back-side power rail and a back-side signal line extending in the first direction in the back-side metal layer.

Abstract: A semiconductor device includes multiple transistors formed in a substrate, a frontside power rail disposed on a frontside of the substrate, and a backside power rail disposed on a backside of the substrate. The transistors form at least a first cell functioning under a first power supply voltage and a second cell functioning under a second power supply voltage that is different from the first power supply voltage. The frontside power rail provides the first power supply voltage to the first cell, and the backside power rail provides the second power supply voltage to the second cell.

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

Abstract: A semiconductor device includes a substrate and a first transistor on a first side of the substrate. The semiconductor device further includes a first electrode contacting a first region of the first transistor. The semiconductor device further includes a spacer extending along a sidewall of the first transistor. The semiconductor device further includes a self-aligned interconnect structure (SIS) separated from at least a portion of the first electrode by the spacer, wherein the SIS extends through the substrate. The semiconductor device further includes a second electrode contacting a surface of the first electrode farthest from the substrate, wherein the second electrode directly contacts the SIS.

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

Abstract: A semiconductor device according to the present disclosure includes an anti-punch-through (APT) region over a substrate, a plurality of channel members over the APT region, a gate structure wrapping around each of the plurality of channel members, a source/drain feature adjacent to the gate structure, and a diffusion retardation layer. The source/drain feature is spaced apart from the APT region by the diffusion retardation layer. The source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer. The diffusion retardation layer is a semiconductor material.