Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

Abstract: The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

Abstract: The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to seamless metallization structures and methods of manufacture. A structure includes: a contact opening formed in an oxide material and in alignment with an underlying structure; a metal liner lining the sidewalls and bottom of the contact opening, in direct electrical contact with the underlying structure; a conductive liner on the metal liner, within the contact opening; and tungsten fill material on the conductive liner and within the contact opening.

Abstract: The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

Abstract: The present invention relates generally to forming interconnects over contacts and more particularly, to a method and structure for filling interconnect trenches with a sacrificial filler material before removal of a hard mask layer to protect the liners of the contacts from damage during the removal process. A method is disclosed that may include: filling an opening in a dielectric layer above a contact and a contact liner with a sacrificial filler material, such that the contact liner is completely covered by the sacrificial filler material; removing a hard mask layer used to pattern and form the opening; and removing the sacrificial filler material from the opening selective to the dielectric layer, the contact liner, and the contact to form an interconnect trench.

Abstract: A set of trenches can be formed in a thin film dielectric layer located on a substrate. The set of trenches can be filled with a predominantly tungsten layer that electrically connects circuit components located on the substrate. The tungsten layer can be recessed below an upper surface of the thin film dielectric layer, while maintaining electrical connection between the circuit components located on the substrate. A liner can be formed over the tungsten layer in the trenches. A metal layer that is predominantly made from a metal other than tungsten, can be formed over the liner.

Abstract: The present invention relates generally to forming interconnects over contacts and more particularly, to a method and structure for filling interconnect trenches with a sacrificial filler material before removal of a hard mask layer to protect the liners of the contacts from damage during the removal process. A method is disclosed that may include: filling an opening in a dielectric layer above a contact and a contact liner with a sacrificial filler material, such that the contact liner is completely covered by the sacrificial filler material; removing a hard mask layer used to pattern and form the opening; and removing the sacrificial filler material from the opening selective to the dielectric layer, the contact liner, and the contact to form an interconnect trench.

Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

Abstract: A post metal chemical-mechanical planarization (CMP) cleaning process for advanced interconnect technology is provided. The process, which follows CMP, combines an acidic clean and a basic clean in sequence. The process can achieve a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. The process also eliminates the circular ring defects that occur intermittently during roller brush cleans within a roller brush clean module.

Abstract: A post metal chemical-mechanical planarization (CMP) cleaning process for advanced interconnect technology is provided. The process, which follows CMP, combines an acidic clean and a basic clean in sequence. The process can achieve a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. The process also eliminates the circular ring defects that occur intermittently during roller brush cleans within a roller brush clean module.

Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

Abstract: Pitch-dependent dishing and erosion following CMP treatment of copper features is quantitatively assessed by atomic force microscopy (AFM) and transmission electron microscopy (TEM). A new sequence of processing steps presented herein is used to prevent dishing and to reduce significantly the local pitch- and pattern density-induced CMP non-uniformity for copper metal lines having widths and spacing in the range of about 32-128 nm. The new process includes a partial copper deposition step followed by deposition of a silicon carbide/nitride (SiCxNy) blocking layer. A multi-step CMP process planarizes areas of the resulting irregular surface that have narrow features, while the blocking layer protects areas that have wide features.

Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

Abstract: The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.