Abstract: An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

Abstract: A method for controlling the shape of copper features, having the following steps:

Abstract: A new class of fluorinated arylacetylene compounds useful as monomers in the formation of polymers having low dielectric constant. These polymers, which are the reaction products of one of the fluorinated arylacetylene compounds, a diphenyl oxide biscyclopentadienone and, optionally, 1,3,5-tris(phenylacetylene)benzene, are useful in insulating microelectric device.

Abstract: A scribe line structure of a semiconductor wafer is provided in the invention. The semiconductor wafer has a plurality of substantially parallel horizontal scribe lines and a plurality of substantially parallel vertical scribe lines to separate a plurality of chips from each other. According to the invention, each parallel horizontal scribe line and each parallel vertical scribe line are divided along two elongated sides thereof into a plurality of portions with the same rectangular area. Each of the plurality of portions of each scribe line is composed of the scribe line structure. The scribe line structure comprises a multi-layer structure with four sides formed over whole area of each portion of each scribe line and at least two rows of cavities formed along the four sides of the multi-layer structure. The cavities of the scribe line structure are capable of relieving internal stress of the scribe lines and arresting possible cracks induced during scribe line manufacture.

Abstract: A scribe line structure of a semiconductor wafer is provided in the invention. The semiconductor wafer has a plurality of substantially parallel horizontal scribe lines and a plurality of substantially parallel vertical scribe lines to separate a plurality of chips from each other. According to the invention, each parallel horizontal scribe line and each parallel vertical scribe line are divided along two elongated sides thereof into a plurality of portions with the same rectangular area. Each of the plurality of portions of each scribe line is composed of the scribe line structure. The scribe line structure comprises a multi-layer structure with four sides formed over whole area of each portion of each scribe line and at least two rows of cavities formed along the four sides of the multi-layer structure. The cavities of the scribe line structure are capable of relieving internal stress of the scribe lines and arresting possible cracks induced during scribe line manufacture.

Abstract: An inter-metal dielectric (IMD) layer structure and its forming method are disclosed. The IMD layer structure is formed between a first conducting layer and a second conducting layer and includes a first dielectric layer overlying the first conducting layer, a glass layer overlying the first dielectric layer, an etching stop layer overlying the glass layer, and a second dielectric layer overlying the etching stop layer under the second conducting layer. The etching rate of the etching stop layer is relatively low so that it can prevent the glass layer etched out. Therefore, a long-time etching can be used to obtain a better through hole profile.

Abstract: A process for forming shallow trench isolation (STI) structures. It includes the steps of: (a) depositing a composite silicon nitride on to the silicon substrate; (b) forming a shallow trench on the silicon substrate by etching, using the composite silicon nitride as the hard mask; (c) depositing a filler oxide layer inside the shallow trench as well as on top of the composite silicon nitride, using a chemical vapor deposition (CVD) method; and (d) using a chemical-mechanical polishing (CMP) process to planarize the filler oxide layer using the composite nitride as a CMP stop. The composite silicon nitride comprises a plurality of silicon nitride layers whose CMP removal rate increases with the distance from the silicon substrate. Additionally, a composite silicon oxide layer can be formed on top of the filler oxide layer which comprises a plurality of silicon oxide layers whose CMP removal rate increases with the distance from the silicon substrate.

Abstract: An improved metal bonding pad is disclosed which can prevent the formation of cracks during the high temperature PECVD deposition, and the subsequent annealing, of a passivation layer which is formed to encroach the metal bonding pad and provide an encapsulation force on the metal bonding pad. The metal bonding pad comprises a plurality of stress bumpers on the periphery thereof. The stress bumpers can be hollow elongated round-cornered rectangles, pin-shaped circles, Y-shaped polygons, or ellipses. The stress bumpers, which create a discontinuous structure in the metal pad, can effectively stop stress propagation as well as relieve and re-direct stress propagation, so as to maintain the integrity of the passivation encroachment and prevent the peeling off problems often observed with the metal bonding pad.

Abstract: This invention provides metallic thin film chemical mechanical polishing slurry compositions having improved suspension stability. The slurry contains 2.5-10% by weight of alumina powder and 2-20% by volume of phosphoric acid (80% concentration ) solution, and using potassium hydroxide to adjust its pH to 1-6 so as to increase suspension ability of the alumina powder in the aqueous slurry. The polishing slurry compositions can further combine with suitable oxidizers such as hydrogen peroxide, ferric nitrate and so on to be appropriately used for chemical mechanical polishing metallic thin film in the process of manufacturing semiconductor in order to control abrasion rate and unevenness more easily.