Patents by Inventor Wei-Tsu Tseng
Wei-Tsu Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130063173Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.Type: ApplicationFiled: September 13, 2012Publication date: March 14, 2013Applicants: IBM Semiconductor Research and Development Center (SRDC), STMicroelectronics, Inc.Inventors: John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng
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Patent number: 8324622Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.Type: GrantFiled: December 31, 2009Date of Patent: December 4, 2012Assignees: STMicroelectronics Inc., International Business Machines CorporationInventors: John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng
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Publication number: 20110156032Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Applicants: STMICROELECTRONICS, INC., IBM Semiconductor Research and Development Center (SRDC)Inventors: John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng
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Patent number: 7556972Abstract: Processes and apparatuses are disclosed for detecting and characterizing SiCOH-based dielectric materials during integrated circuit fabrication. The processes generally include chromatographically analyzing a fluid stream generated during a process employed for device fabrication, e.g., during a wet strip, a chemical mechanical planarization process and the like.Type: GrantFiled: January 25, 2007Date of Patent: July 7, 2009Assignee: International Business Machines CorporationInventors: Manoj Balachandran, James A. Hagan, Ben Kim, Deoram Persaud, Adam D. Ticknor, Wei-tsu Tseng
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Patent number: 7510463Abstract: The present invention is an apparatus and method for extending the life of abrasive disks used in the conditioning of polishing pads used in chemical mechanical planarization (CMP) of polishing pads used to polish and/or planarize the surfaces of semiconductor wafers during the production of integrated circuits. The invention consists of the a disk comprising a plurality of abrasive segments, each of which is fixed in tangential and radial relationship to one another about the common axis of rotation of the conditioning disk. Means are provided for movement of the abrasive segments, individually or in sets, into or out of the plane of the active abrasive surface of the conditioning disk according to the present invention.Type: GrantFiled: June 7, 2006Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: Ben Kim, Manoj Balachandran, James Aloysius Hagan, Deoram Persaud, Adam Daniel Ticknor, Wei-tsu Tseng
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Patent number: 7407879Abstract: An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.Type: GrantFiled: March 7, 2006Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Lee M Nicholson, Wei-Tsu Tseng, Christy S Tyberg
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Publication number: 20080182335Abstract: Processes and apparatuses are disclosed for detecting and characterizing SiCOH-based dielectric materials during integrated circuit fabrication. The processes generally include chromatographically analyzing a fluid stream generated during a process employed for device fabrication, e.g., during a wet strip, a chemical mechanical planarization process and the like.Type: ApplicationFiled: January 25, 2007Publication date: July 31, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manoj Balachandran, James A. Hagan, Ben Kim, Deoram Persaud, Adam D. Ticknor, Wei-Tsu Tseng
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Publication number: 20070287367Abstract: The present invention is an apparatus and method for extending the life of abrasive disks used in the conditioning of polishing pads used in chemical mechanical planarization (CMP) of polishing pads used to polish and/or planarize the surfaces of semiconductor wafers during the production of integrated circuits. The invention consists of the a disk comprising a plurality of abrasive segments, each of which is fixed in tangential and radial relationship to one another about the common axis of rotation of the conditioning disk. Means are provided for movement of the abrasive segments, individually or in sets, into or out of the plane of the active abrasive surface of the conditioning disk according to the present invention.Type: ApplicationFiled: June 7, 2006Publication date: December 13, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ben Kim, Manoj Balachandran, James Aloysius Hagan, Deoram Persaud, Adam Daniel Ticknor, Wei-tsu Tseng
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Publication number: 20070190788Abstract: Reduction of a wafer removing force on a chemical mechanical planarization (CMP) tool that includes planarizing a wafer on a platen at a wafer/platen interface; applying carbonated water to the wafer/platen interface so as to reduce the removing force; and removing the wafer from the platen.Type: ApplicationFiled: February 15, 2006Publication date: August 16, 2007Inventors: Manoj Balachandran, James Hagan, Ben Kim, Deoram Persaud, Adam Ticknor, Wei-Tsu Tseng
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Patent number: 7253098Abstract: A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.Type: GrantFiled: August 27, 2004Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Shyng-Tsong T. Chen, Kaushik Arun Kumar, Stephen Edward Greco, Shom Ponoth, Terry Allen Spooner, David L. Rath, Wei-Tsu Tseng
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Patent number: 7190079Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.Type: GrantFiled: November 3, 2005Date of Patent: March 13, 2007Assignee: International Business Machines CorporationInventors: Panayotis C. Andricacos, Shyng-Tsong Chen, John M. Cotte, Hariklia Deligianni, Mahadevaiyer Krishnan, Wei-Tsu Tseng, Philippe M. Vereecken
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Publication number: 20060166012Abstract: An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.Type: ApplicationFiled: March 7, 2006Publication date: July 27, 2006Inventors: Lee Nicholson, Wei-Tsu Tseng, Christy Tyberg
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Patent number: 7071539Abstract: An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.Type: GrantFiled: July 28, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Lee M Nicholson, Wei-Tsu Tseng, Christy S Tyberg
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Patent number: 7064064Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: GrantFiled: February 16, 2005Date of Patent: June 20, 2006Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin, Steffen K. Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael F. Lofaro, Sandra G. Malhotra, Chandrasekhar Narayan, David L. Rath, Judith M. Rubino, Katherine L. Saenger, Andrew H. Simon, Sean P. E. Smith, Wei-tsu Tseng
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Publication number: 20060105676Abstract: A signal processing system has the detected mechanical, chemical, optical, electrical, or thermal signals generated during chemical-mechanical polishing (CMP) process collected, analyzed and differentiated with respect to time in-situ, in order to reveal the different stages during CMP for process control and end-pointing purposes. This control and/or end-pointing scheme may be used to detect the interface between two material layers sharing similar properties such as those of low-k dielectric stacks for semiconductor applications.Type: ApplicationFiled: November 17, 2004Publication date: May 18, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eugene O'Sullivan, Shom Ponoth, Wei-Tsu Tseng
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Publication number: 20060076685Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.Type: ApplicationFiled: November 3, 2005Publication date: April 13, 2006Applicant: International Business MachinesInventors: Panayotis Andricacos, Shyng-Tsong Chen, John Cotte, Hariklia Deligianni, Mahadevaiyer Krishnan, Wei-Tsu Tseng, Philippe Vereecken
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Patent number: 7008871Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.Type: GrantFiled: July 3, 2003Date of Patent: March 7, 2006Assignee: International Business Machines CorporationInventors: Panayotis C. Andricacos, Shyng-Tsong Chen, John M. Cotte, Hariklia Deligianni, Mahadevaiyer Krishnan, Wei-Tsu Tseng, Philippe M. Vereecken
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Publication number: 20060043590Abstract: A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.Type: ApplicationFiled: August 27, 2004Publication date: March 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven Shyng-Tsong Chen, Kaushik Kumar, Stephen Greco, Shom Ponoth, Terry Spooner, David Rath, Wei-Tsu Tseng
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Patent number: 6975032Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: GrantFiled: December 16, 2002Date of Patent: December 13, 2005Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin, Steffen K. Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael F. Lofaro, Sandra G. Malhotra, Chandrasekhar Narayan, David L. Rath, Judith M. Rubino, Katherine L. Saenger, Andrew H. Simon, Sean P. E. Smith, Wei-tsu Tseng
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Publication number: 20050158985Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: ApplicationFiled: February 16, 2005Publication date: July 21, 2005Inventors: Shyng-Tsong Chen, Timothy Dalton, Kenneth Davis, Chao-Kun Hu, Fen Jamin, Steffen Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael Lofaro, Sandra Malhotra, Chandrasekhar Narayan, David Rath, Judith Rubino, Katherine Saenger, Andrew Simon, Sean Smith, Wei-tsu Tseng