Abstract: A display apparatus including a display panel and a driver circuit is provided. The display panel includes a display region and a non-display region. The non-display region includes a plurality of dummy pixels connected to one another. The driver circuit provides gate driving voltages and a test data voltage, so as to make the dummy pixels connected to one another generate a charging rate test signal in response to the test data voltage.

Abstract: A sensitive device includes a plurality of first conductive nanostructures, a conductive layer and at least one electrode. The conductive layer covers the first conductive nanostructures. An intrinsic melting point of the conductive layer is higher than that of the first conductive nanostructures. At least one of the conductive layer and the first conductive nanostructures is sensitive to gas. The electrode is electrically connected to at least one of the first conductive nanostructures and the conductive layer.

Abstract: A display apparatus includes at least one pixel structure, which includes an active device, an electric insulation layer and a pixel electrode. The electric insulation layer is disposed on the active device. The electric insulation layer has a trench and a via. The via is located on a bottom surface of the trench. A portion of the electric insulation layer surrounding the trench is monolithically connected to another portion of the electric insulation layer surrounding the via. A pixel electrode has a first electrode portion and a second electrode portion connected to each other. The first electrode portion is located in the trench. A thickness of the first electrode portion is less than a depth of the trench. The second electrode portion is located in the via and is electrically connected to the active device through the via.

Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.

Abstract: A vertical transistor and a manufacturing method thereof are provided herein. The manufacturing method includes forming a first patterned conductive layer on a substrate; forming a patterned metal oxide layer on the first patterned conductive layer, in which the patterned metal oxide layer includes a first patterned insulator layer, a second patterned insulator layer, and a second patterned conductive layer; forming a semiconductor layer; and forming a third patterned conductive layer. The first patterned insulator layer, the second patterned insulator layer, and the second patterned conductive layer are made by using a single metal oxide material. The oxygen concentration of the second patterned conductive layer is different from the oxygen concentrations of the first patterned insulator layer and the second patterned insulator layer.

Abstract: A manufacturing method of a transistor is provided, and the method includes: providing a base; forming a fin-shaped gate on the base; covering the fin-shaped gate with an insulation layer; providing a substrate; forming a partially cured sol-gel on the substrate; inserting the fin-shaped gate into the partially cured sol-gel, so that a portion of the fin-shaped gate is uncovered by the partially cured sol-gel; after inserting the fin-shaped gate into the partially cured sol-gel, curing the partially cured sol-gel; and processing a portion of the partially cured sol-gel not overlapping with the fin-shaped gate to increase conductivity of the portion of the partially cured sol-gel.

Abstract: A semiconductor structure includes a top gate, an oxide semiconductor channel layer, a first dielectric layer, a second dielectric layer, a source and a drain. The oxide semiconductor channel layer is disposed between the top gate and a substrate. The first dielectric layer is disposed between the top gate and the oxide semiconductor channel layer. The second dielectric layer is disposed between the first dielectric layer and the oxide semiconductor channel layer. The source and the drain are disposed on two opposite sides of the oxide semiconductor channel layer and located between the first dielectric layer and the substrate. A portion of the oxide semiconductor channel layer is exposed between the source and the drain. A portion of the first dielectric layer and a portion of the second dielectric layer directly contact with and entirely cover the portion of the oxide semiconductor channel layer.

Abstract: A thin film transistor (TFT) including a gate, a dielectric layer, a metal-oxide semiconductor channel, a source, and a drain is provided. The gate and the metal-oxide semiconductor channel are overlapped. The gate, the source, and the drain are separated by the dielectric layer. Besides, the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel. The metal-oxide semiconductor channel includes a metal-oxide semiconductor layer and a plurality of nano micro structures disposed in the metal-oxide semiconductor layer and separated from one another. In another aspect, a display panel including the TFT and a method of fabricating the TFT are also provided.

Abstract: A capacitor structure of capacitive touch panel including a first electrode layer, a first material layer, a second material layer and a second electrode layer is provided. The first material layer is disposed on the first electrode layer, and the material of the first material layer is selected from one of a semiconductor material and an insulating material. The second material layer is disposed on the first material layer, and the material of the second material layer is selected from another one of the semiconductor material and the insulating material. The second electrode layer is disposed on the second material layer.

Abstract: A transistor including a substrate, a source, a drain, an active portion, a fin-shaped gate, and an insulation layer is provided. The source is located on the substrate. The drain is located on the substrate. The active portion connects the source and the drain. The fin-shaped gate wraps the active portion. A first portion of the insulation layer separates the fin-shaped gate from the active portion, a second portion of the insulation layer separates the fin-shaped gate from the substrate, a third portion of the insulation layer separates the fin-shaped gate from the source and from the drain, and a fourth portion of the insulation layer is located on a surface of the fin-shaped gate facing away from the active portion. The insulation layer is integrally formed. A manufacturing method of a transistor is also provided.

Abstract: An active device provided by the invention is disposed on a substrate and includes a gate, a gate insulating layer, an oxide semiconductor channel layer, a plurality of nano conductive wires, a source and a drain. The gate insulating layer is disposed between the gate and the oxide semiconductor channel layer. The nano conductive wires are distributed in the oxide semiconductor channel layer, in which the nano conductive wires do not contact the gate insulating layer and the nano conductive wires are arranged along a direction and not intersected with each other. The source and the drain are disposed on two sides opposite to each other of the oxide semiconductor channel layer, in which a portion of the oxide semiconductor channel layer is exposed between the source and the drain.

Abstract: A light sensitive display apparatus and an operating method thereof are disclosed herein. The light sensitive display apparatus includes a plurality of pixels, and the operating method of the light sensitive display apparatus includes the following steps. In a writing state, a first data voltage and a first gate voltage are provided to the pixels, and the pixels illuminated by light rays are switched to or kept in a first display state. In an erasing state, a second data voltage and a second gate voltage are provided to the pixels, and the pixels illuminated by light rays are switched to or kept in a second display state.

Abstract: A thin film transistor structure including a substrate, a gate, an oxide semiconductor layer, a gate insulation layer, a source, a drain, a silicon-containing light absorption layer and an insulation layer is provided. The gate insulation layer is disposed between the oxide semiconductor layer and the gate. The oxide semiconductor layer and the gate are stacked in a thickness direction. The source and the drain contact the oxide semiconductor layer. A portion of the oxide semiconductor layer without contacting the source and the drain defines a channel region located between the source and the drain. The oxide semiconductor layer is located between the substrate and the silicon-containing light absorption layer. The silicon-containing light absorption layer has a band gap smaller than 2.5 eV. The insulation layer is disposed between the oxide semiconductor layer and the silicon-containing light absorption layer, and in contact with the silicon-containing light absorption layer.

Abstract: A thin film transistor and a fabrication method thereof are provided. A metal patterning layer is formed on the metal oxide semiconductor layer of a thin film transistor to shield the metal oxide semiconductor layer from the water, oxygen and light in the environment.

Abstract: A semiconductor structure includes a top gate, an oxide semiconductor channel layer, a first dielectric layer, a second dielectric layer, a source and a drain. The oxide semiconductor channel layer is disposed between the top gate and a substrate. The first dielectric layer is disposed between the top gate and the oxide semiconductor channel layer. The second dielectric layer is disposed between the first dielectric layer and the oxide semiconductor channel layer. The source and the drain are disposed on two opposite sides of the oxide semiconductor channel layer and located between the first dielectric layer and the substrate. A portion of the oxide semiconductor channel layer is exposed between the source and the drain. A portion of the first dielectric layer and a portion of the second dielectric layer directly contact with and entirely cover the portion of the oxide semiconductor channel layer.

Abstract: A light sensor including a photo transistor is provided. A gate of the photo transistor receives a gate driving signal. The photo transistor senses a light source based on the gate driving signal to generate a light current signal. The photo transistor includes a metal-oxide active layer. The gate driving signal has a first voltage level during a trap period and has a second voltage level during a read period. The first voltage level is higher than the second voltage level. The gate driving signal of the photo transistor introduces a mechanism to rapidly eliminate excess carriers. Accordingly, the photo transistor has a rapid response while maintaining good light responsibility. Furthermore, a method for driving the foregoing photo transistor is also provided.

Abstract: An active device includes a gate, a gate insulation layer, a channel layer, a first passivation layer, a second passivation layer, a source and a drain. The gate insulation layer is disposed on the substrate and covers the gate. The channel layer is disposed on the gate insulation layer and has a semiconductor section disposed corresponding to the gate and a conductive section located around the semiconductor section. The first passivation layer is disposed on the channel layer and covers the semiconductor section. The second passivation layer is disposed on and covers the first passivation layer. The source and the drain are disposed on the gate insulation layer, and extended along peripheries of the conductive section, the first and the second passivation layers to be disposed on the second passivation layer. A portion of the second passivation layer is exposed between the source and the drain.

Abstract: A vertical transistor and a manufacturing method thereof are provided herein. The manufacturing method includes forming a first patterned conductive layer on a substrate; forming a patterned metal oxide layer on the first patterned conductive layer, in which the patterned metal oxide layer includes a first patterned insulator layer, a second patterned insulator layer, and a second patterned conductive layer; forming a semiconductor layer; and forming a third patterned conductive layer. The first patterned insulator layer, the second patterned insulator layer, and the second patterned conductive layer are made by using a single metal oxide material. The oxygen concentration of the second patterned conductive layer is different from the oxygen concentrations of the first patterned insulator layer and the second patterned insulator layer.

Abstract: An active device provided by the invention is disposed on a substrate and includes a gate, a gate insulating layer, an oxide semiconductor channel layer, a plurality of nano conductive wires, a source and a drain. The gate insulating layer is disposed between the gate and the oxide semiconductor channel layer. The nano conductive wires are distributed in the oxide semiconductor channel layer, in which the nano conductive wires do not contact the gate insulating layer and the nano conductive wires are arranged along a direction and not intersected with each other. The source and the drain are disposed on two sides opposite to each other of the oxide semiconductor channel layer, in which a portion of the oxide semiconductor channel layer is exposed between the source and the drain.

Abstract: A thin film transistor structure is provided. The thin film transistor structure includes a first transistor having a first active layer, a second transistor having a second active layer, a first protection layer contacting the first active layer, and a second protection layer contacting the second active layer. The oxygen contents of the first and the second protection layers are controlled to affect the oxygen vacancy number of the first and the second active layers to satisfy the various electronic requirements of the first and the second transistors.