Abstract: A method of performing inter-picture prediction of a current picture of a video sequence is performed by at least one processor and includes determining whether the current picture uses a virtual reference picture, and based on the current picture being determined to use the virtual reference picture, generating, for the current picture, the virtual reference picture from neighboring reference pictures that are nearest neighbors to the virtual reference picture, storing the generated virtual reference picture in a decoded picture buffer, and adding the generated virtual reference picture to an active reference picture list. The method further includes performing the inter-picture prediction of the current picture, based on the active reference picture list to which the virtual reference picture is added.

Abstract: Embodiments of the present disclosure provide a method of backup management, an electronic device and a computer program product. The method comprises: determining a plurality of candidate backup policies for a plurality of clients of a data backup system, determining an expected load balance degree with respect to time for the data backup system to perform data backups for the plurality of clients using the plurality of candidate backup policies, determining an actual load balance degree with respect to time for the data backup system while the data backup system is performing the data backups for the plurality of clients using a plurality of current backup policies, and selecting a plurality of backup policies to be used for the plurality of clients respectively, based on a comparison of the expected load balance degree and the actual load balance degree.

Abstract: Aspects of the disclosure provide a method, an apparatus, and a non-transitory computer-readable storage medium for video decoding. The apparatus can include processing circuitry. The processing circuitry is configured to reconstruct blocks of an image from a coded video bitstream. The processing circuitry can perform post-processing on one of a plurality of regions of first two neighboring reconstructed blocks of the reconstructed blocks with at least one post-processing neural network (NN). The first two neighboring reconstructed blocks have a first shared boundary and include a boundary region having samples on both sides of the first shared boundary. The plurality of regions of the first two neighboring reconstructed blocks includes the boundary region and non-boundary regions that are outside the boundary region. The one of the plurality of regions is replaced with the post-processed one of the plurality of regions of the first two neighboring reconstructed blocks.

Abstract: A three section foldable bed includes a plurality of boards comprising an upper board, a middle board, and a lower board; a support assembly for supporting the plurality of boards, wherein the support assembly includes a first support structure for supporting the upper board, a second support structure for supporting the middle board, and a third support structure for supporting the lower board; a pair of first connection mechanisms for connecting the first support structure and the second support structure such that the first support structure and the second support structure are pivotally foldable relative to one another at the pair of first connection mechanisms; and a pair of second connection mechanisms for connecting the second support structure and the third support structure such that the second support structure and the third support structure are pivotally foldable relative to one another at the pair of second connection mechanisms.

Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.

Abstract: A conductive structure, a semiconductor package and methods of forming the same are disclosed. A conductive structure includes a metal feature, an insulating layer and a nitridized metal layer. The metal feature is disposed over a substrate and includes a lower metal pattern and an upper metal pattern over the lower metal pattern. The insulating layer surrounds the metal feature. The nitridized metal layer is disposed between the lower metal pattern and the upper metal pattern.

Abstract: Described are methods for preparing a deuterated aldehyde using N-heterocyclic carbene catalysts in a solvent comprising D2O. The methods may be used to convert a wide variety of aldehydes (e.g., aryl, alkyl, or alkenyl aldehydes) to C-1 deuterated aldehydes under mild reaction conditions without functionality manipulation.

Abstract: A physical vapor deposition (PVD) system is provided. The PVD system includes a PVD chamber defining a PVD volume within which a target material of a target is deposited onto a wafer. The PVD system includes the target in the PVD chamber. The target is configured to overlie the wafer. An edge of the target extends from a first surface of the target to a second surface of the target, opposite the first surface of the target. A first portion of the edge of the target has a first surface roughness. The first portion of the edge of the target extends at most about 6 millimeters from the first surface of the target to a second portion of the edge of the target. The second portion of the edge of the target has a second surface roughness less than the first surface roughness.

Abstract: Provided are isolated polynucleotides and recombinant DNA constructs encoding polypeptides useful for conferring accelerated or delayed flowering time and/or maturity. Compositions (such as plants or seeds) comprising these recombinant DNA constructs; and methods utilizing these recombinant DNA constructs are also provided.

Abstract: This application discloses a laser detection apparatus, a method for manufacturing the laser detection apparatus, and a terminal, and belongs to the field of laser detection technologies, for example, light detection and ranging (Lidar). The apparatus includes a multiphase signal generation circuit, an amplifier array, and a laser transmitter array. The amplifier array includes a plurality of first amplifiers, and the laser transmitter array includes a plurality of laser transmitters. A plurality of output ends of the multiphase signal generation circuit are connected to input ends of corresponding first amplifiers, and output ends of the plurality of first amplifiers are connected to corresponding laser transmitters.

Abstract: A foldable bed includes a plurality of boards comprising an upper board, a middle board, and a lower board; a support assembly for supporting the plurality of boards, wherein the support assembly includes a first support structure for supporting the upper board and the middle board, and a second support structure for supporting the lower board; and a pair of connection mechanisms for connecting the first support structure and the second support structure such that the first support structure and the second support structure are pivotally foldable relative to one another at the pair of connection mechanisms.

Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

Abstract: A method includes disposing, by using a transport module of a workpiece storage system, a first workpiece on a first workpiece carrier; disposing, by using the transport module, the first workpiece carrier with the first workpiece in a workpiece container; disposing, by using the transport module, a second workpiece in the workpiece container, wherein the first workpiece and the second workpiece have different sizes; and transferring, by using the transport module, the workpiece container containing the second workpiece and the first workpiece carrier with the first workpiece to a stocker to store the workpiece container.

Abstract: A microfluidic apparatus is provided. The microfluidic apparatus includes a base substrate; a microfluidic device on the base substrate and including a plurality of micro fluidic channels; a plurality of light sources of different colors respectively emitting light of different wavelength ranges; a light extraction apparatus for extracting light respectively from the plurality of light sources of different colors and a plurality of photosensors. The light extraction apparatus includes a light guide plate having a plurality of light incident portions for respectively receiving light respectively incident from the plurality of light sources of different colors, the plurality of light incident portions being on a side of the light guide plate away from the microfluidic device; and a plurality of light extractors on the light guide plate.

Abstract: A method, computer program, and computer system is provided for compressing a neural network model. One or more coding tree units are identified corresponding to a multi-dimensional tensor associated with a neural network. A set of weight coefficients associated with the coding tree units is unified. A model of the neural network is compressed based on the unified set of weight coefficients.

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

Abstract: An apparatus of neural network model decompression includes processing circuitry. The processing circuitry can be configured to receive, from a bitstream of a compressed neural network representation, one or more first syntax elements associated with a 3-dimensional coding unit (CU3D) partitioned from a 3-dimensional coding tree unit (CTU3D). The first CTU3D can be partitioned from a tensor in a neural network. The one or more first syntax elements can indicate that the CU3D is partitioned based on a 3D pyramid structure that includes multiple depths. Each depth corresponds to one or more nodes. Each node has a node value. Second syntax elements corresponding to the node values of the nodes in the 3D pyramid structure can be received from the bitstream in a breadth-first scan order for scanning the nodes in the 3D pyramid structure. Model parameters of the tensor can be reconstructed based on the received second syntax elements.

Abstract: Silicon particles for active materials and electro-chemical cells are provided. The active materials comprising silicon particles described herein can be utilized as an electrode material for a battery. In certain embodiments, the composite material includes greater than 0% and less than about 90% by weight silicon particles, the silicon particles having an average particle size between about 10 nm and about 40 ?m, wherein the silicon particles have surface coatings comprising silicon carbide or a mixture of carbon and silicon carbide, and greater than 0% and less than about 90% by weight of one or more types of carbon phases, wherein at least one of the one or more types of carbon phases is a substantially continuous phase.

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

Abstract: Aspects of the disclosure provide methods, apparatuses, and a non-transitory computer-readable storage medium for video encoding and video decoding. An apparatus for video decoding can include processing circuitry. The processing circuitry is configured to decode neural network update information in a coded bitstream for at least one neural network in the video decoder. The at least one neural network is configured with a set of pretrained parameters, and the neural network update information indicates a first modification parameter. The processing circuitry is configured to update the set of pretrained parameters in the at least one neural network in the video decoder based on the first modification parameter. The processing circuitry is configured to decode an encoded image based on the updated at least one neural network.