Abstract: First of all, a semiconductor substrate is provided. Then a gate oxide layer having an uniform thickness is formed on the semiconductor substrate by way of using thermal oxidation. Subsequently, a doping layer is formed on the gate oxide layer by a plasma doped process. Next, forming a poly-layer on the doping layer of the gate oxide layer, wherein the poly-layer has an ions-distribution. Afterward, defining the poly-layer to form a poly-gate. The P-type ions are then implanted into the poly-gate and the substrate by way of using a self-aligned process. Finally, performing a thermal annealing process to form a uniform ion-implanting region and a poly-gate having a lower contact-resistance.

Abstract: The present invention provides multiple gate oxide layers with different thicknesses on a semiconductor substrate in an oxygen ion implantation process. The semiconductor substrate comprises a silicon surface, comprising at least a first area and a second area. A first mask layer, having a first opening to expose portions of the silicon surface in the first area, is formed on the silicon surface to cover surfaces of both the first area and the second area. An oxygen ion implantation process is then performed to implant oxygen ions with a predetermined concentration into the first area through the first opening. Then the first mask layer is removed. Finally, an oxidation process is performed to simultaneously form a silicon oxide layer with a first predetermined thickness on portions of the silicon surface in the first area and a silicon oxide layer with a second predetermined thickness on portions of the silicon surface in the second area.

Abstract: The present invention provides a method of forming different thickness” of a gate oxide layer simultaneously, by employing a pulse Nitrogen plasma implantation. The method provides a semiconductor substrate with the surface of the silicon in the semiconductor substrate separated into a first region and a second region at least. Then a thin surface on the surface of the silicon of the first region is implanted using a first predetermined concentration of the Nitrogen ions. The thin surface on the surface of the silicon in the second region is implanted using a second predetermined concentration of the Nitrogen ions. An oxidation process is subsequently performed. The first predetermined thickness and the second predetermined thickness of the silicon oxide layer are formed simultaneously on the surface of the silicon in the first region and in the second region. The Nitrogen ions are implanted in the surface of the silicon by forming the pulse nitrogen plasma in-situ.

Abstract: A method for suppressing boron penetrating the gate dielectric layer by pulsed nitrogen plasma doping. A pulsed nitrogen plasma doping process is utilized to dope nitrogen ions into the surface layer in the channel region of the semiconductor substrate. A thermal oxidation step is then performed to form a gate dielectric layer commixed with oxide and oxynitride over the channel region of the semiconductor substrate to avoid boron penetration effect accruing while a boron doped polysilicon layer is subsequently formed on the gate dielectric layer.

Abstract: This invention relates to a method for forming a buffer layer, more particularly, to the method for forming a mixed layer which comprises silicon oxynitride and silicon dioxide to be a buffer layer over a polysilicon gate by using a nitrogen ions implantation and a thermal oxidation. The present invention uses the ions implantation to implant nitrogen ions to the surface of the polysilicon gate at first. After passing through a thermal oxide process, the hard mixed layer, which comprises silicon oxynitride and silicon dioxide, is formed over the surface of the polysilicon gate. The mixed layer, which comprises silicon oxynitride and silicon dioxide, formed over the polysilicon gate can prevent another ions entering to the polysilicon gate to affect the critical dimention of the polysilicon gate.

Abstract: A method for controlling multiple gate oxide growing by argon plasma doping. An argon plasma doping process is utilized to dope argon ions into the surface layer in the channel region of semiconductor substrate. A thermal oxidation step is then performed to form a gate oxide layer on the semiconductor substrate. Since argon ions doping will increase growing thickness of gate oxide, multiple thickness of gate oxide can be produced in one thermal oxidation step by doping different dosage of argon ions in each channel region. Accordingly, using of thermal oxidation step is decreased to shorten process time and therefore increases throughput.

Abstract: A method for forming a liner layer in silicon nitride spacers is disclosed. The method provides a semiconductor substrate having a polysilicon gate structure thereon. Then, as a key step of the present invention is forming a silicon oxynitride layer on the polysilicon gate structure and thereafter a silicon oxide layer is formed on the silicon oxynitride layer. Next, a conformal silicon nitride layer is formed on the semiconductor substrate and the silicon oxide layer. Moreover, on the sides of the silicon oxide layer, the spacers of silicon nitride are formed by anisotropically etching the silicon nitride layer.

Abstract: A method of forming a gate structure. A gate dielectric layer and a polysilicon gate are sequentially formed over a substrate. The substrate is enclosed within a chamber and surrounded by oxygen-containing plasma. A negative voltage is applied to the substrate so that the oxygen ions of the oxygen-containing plasma are implanted into a superficial layer of the polysilicon gate. An annealing operation is conducted in an inert atmosphere so that the implanted oxygen ions in the polysilicon gate react with silicon to form a silicon oxide buffer layer. Finally, spacers are formed on the external sidewall of the silicon oxide buffer layers next to the polysilicon gate.

Abstract: A method for forming shallow trench isolation is disclosed. A pad oxide layer and a mask layer are sequentially formed on a substrate. Afterwards, an opening is formed through the mask layer and the pad oxide layer such that regions of the substrate are exposed. Thereafter, the exposed regions are etched to form trenches inside said substrate. Next, nitrogen ions are implanted into the sidewall of the trenches to form a silicon nitride layer, and then a siliconoxynitride layer is formed inside the sidewall of the trenches. Subsequently, a silicon oxide layer is formed on the siliconoxynitride layer and on the mask layer. The excess portion of the silicon oxide layer over said mask layer is removed to expose the mask layer, and then the mask layer is removed away. Finally, the pad oxide layer is removed by using hydrofluoric acid (HF).

Abstract: This invention relates to a method for forming a shallow junction, more particularly, to the method for forming a ultra-shallow junction by using a arsenic plasma doping fashion. The present invention uses the arsenic plasma doping fashion to dope arsenic ions to the junction of the semiconductor and then passes through a post anneal process. The resistance value of the junction can be controlled. The present invention also uses the depth of doped arsenic ions to control the depth of the junction and to restrain the diffusion of the arsenic ions. Then the region of the junction can be reduced successfully to become a ultra-shallow junction. This ultra-shallow junction is a low resistance value and excellent electricity junction.

Abstract: A boron difluoride plasma doping method to form an ultra-shallow junction. A semiconductor substrate is put inside a reaction chamber and then a boron difluoride ions (BF2+) containing plasma is generated inside the chamber. A negative voltage is applied to the semiconductor substrate so that the boron difloride ions (BF2+) accelerate and bombard against the semiconductor substrate to form an ultra-shallow junction on a superficial layer of the substrate. A rapid annealing operation is conducted to repair any defects in the crystal lattice that results from the formation of the ultra-shallow junction.

Abstract: A method for determining near-surface doping concentration is provided by utilizing surface photovoltage. A monochromatic light pulse is applied to a semiconductor substrate. When the energy of the incident light is larger than the energy gap of the semiconductor substrate, the light is absorbed by the substrate and thereby generates enough charge carriers. The carriers diffuse to the surface of the substrate and result in lowering the surface barrier, and hence, cause a shift of the surface voltage. The difference of the surface voltages, before and after the light pulse applied, is measured by using a surface photovoltage probe. Then, the doping concentration near the surface of the substrate can be determined according to the difference of the surface voltage.

Abstract: A method for suppressing boron penetrating the gate dielectric layer by pulsed nitrogen plasma doping. A pulsed nitrogen plasma doping process is utilized to dope nitrogen ions into the surface layer in the channel region of the semiconductor substrate. A thermal oxidation step is then performed to form a gate dielectric layer commixed with oxide and oxynitride over the channel region of the semiconductor substrate to avoid boron penetration effect accruing while a boron doped polysilicon layer is subsequently formed on the gate dielectric layer.

Abstract: An improved structure heat dissipater for computer central processing units (CPU) having heat sink grid elements perforated with through-holes. The structure of the present invention is comprised of a ventilated hood, heat sink grid elements, and a base plate. The ventilated hood has a plurality of vent holes formed in its top and two lateral surfaces that are aligned with the through-holes in the heat sink grid elements which are interlocked together into a stacked heat sink grid element assembly, thereby forming a honeycomb-like convectionary heat dissipating network of openings. As a result, when air is induced by a fan, air flows through efficiently and rapidly such that heat transfer and diffusion is accelerated from the upper, front, rear, left, and right surfaces, which enhances the overall rate of heat dissipation, effectively improves the removal of heat generated by the CPU, and increases fan performance.