Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

Abstract: A method of forming an AFX zeolite in a hydrothermal synthesis that exhibits a silica to alumina (SiO2AI2O3) molar ratio (SAR) that is between 8:1 and 26:1; has a morphology that includes one or more of cubic, spheroidal, or rhombic particles with a crystal size that is in the range of about 0.1 micrometer (?m) to 10 ?m. This AFX zeolite also exhibits a Brönsted acidity that is in the range of 1.2 mmol/g to 3.6 mmol/g as measured by ammonia temperature programmed desorption. A catalyst formed by substituting a metal into the framework of the zeolite exhibits about a 100% conversion of NO emissions over the temperature range of 300° C. to 650° C.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.

Abstract: A package includes a first molding compound layer, a conductive via embedded in the first molding compound layer, a semiconductor device, a redistribution structure and a second molding compound layer. The semiconductor device and the redistribution structure are respectively disposed on opposite sides of the first molding compound layer, wherein the semiconductor device is electrically connected to the redistribution structure through the conductive via. The second molding compound layer is disposed on the first molding compound layer, wherein the semiconductor device is encapsulated by the second molding compound layer.

Abstract: A device for shaping an angle of a guide wire includes a support platform configured to provide a support surface for placing the guide wire, and an angled cutter head configured to press and bend the guide wire at an accurate angle. A method for shaping with a device for shaping an angle of a guide wire includes the following steps: placing a guide wire on a support platform, extending out the guide wire by a certain bending length, pressing down on the guide wire with an angled cutter head of which the bottom surface is provided with a certain angle, and preparing the guide wire of which one end has an angle of required accuracy.

Abstract: A multimedia system is provided. The multimedia system includes a plurality of transmission devices and a receiving-end device. Multiple transmission devices respectively has a microphone. The receiving-end device is coupled to the transmission devices. When the microphone of one of the transmission devices is enabled, the receiving-end device outputs at least one control signal to at least another one of the transmission devices to disable the microphone of the at least another one of the transmission devices.

Abstract: Disclosed are a semiconductor package and a manufacturing method of a semiconductor package. In one embodiment, the semiconductor package includes an interposer substrate, a plurality of semiconductor dies, one or more heat dissipation elements and an encapsulant. The plurality of semiconductor dies are disposed on the interposer substrate. The one or more heat dissipation elements are disposed on the plurality of semiconductor dies. The encapsulant is disposed on the interposer substrate and surrounds the plurality of semiconductor dies and the one or more heat dissipation elements.

Abstract: A photovoltaic inverter includes a casing, at least one circuit board located in the casing, a current sensor located on the at least one circuit board, an arc detector located on the at least one circuit board, a self-test coil located on the at least one circuit board, and at least one direct current input terminal located on the casing and connected to the at least one circuit board, wherein the self-test coil is configured to deliver a test signal to be sensed by the arc detector, and the direct current input terminal is configured to deliver a direct current through the arc detector, wherein the current sensor is configured to detect a magnitude of the direct current passing through the direct current input terminal.

Abstract: A method for predicting an attacked path on enterprise networks includes: obtaining a plurality of accounts, a plurality of machines and network resource data, where the plurality of machines include at least one attacked target; calculating, according to the network resource data, a plurality of evaluated values of executing access on other machines of each account logging in at least one machine; and presenting an attacked path where a machine at least one account logs in accesses the attacked target directly, or indirectly by connecting to other machines, and the machine the at least one account logs in points to the attacked target directly, or indirectly by connecting to other machines.

Abstract: A digital control method is to accurately calculate the real-time addition amount of each dye in the solution replenishment system in the whole dyeing process based on the initial dyeing rate of each dye, and replenish the dye solution according to the real-time addition amount. A digital control system includes an automatic calculation K0,n value unit, a central processing unit and a replenishment pump. The automatic calculation K0,n value unit is composed of a dye solution concentration detection instrument, a sensor I and a BP neural network model. The BP neural network model is a BP neural network trained by a dye database. The automatic calculation K0,n value unit transmits the K0,n value to the central processing unit, calculates the replenishment amount through the central processing unit, and controls the replenishment pump to replenish the solution.

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first microelectronic elements on a first temporary substrate; and replacing at least one defective microelectronic element of the first microelectronic elements with at least one second microelectronic element. The first microelectronic elements and at least one second microelectronic element are distributed on the first temporary substrate. The first microelectronic elements and at least one second microelectronic element have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first microelectronic elements and at least one second microelectronic element. A semiconductor structure and a display panel are also provided.

Abstract: An image processing circuit includes a first buffer circuit, a first selector circuit, a processor circuit, a second buffer circuit, and an assigning circuit. The first buffer circuit receives pixels in a sliding window of an image. The first selector circuit outputs the pixels according to a mode signal. The processor circuit performs a first filtering process on the pixels to generate first processed pixels. The assigning circuit transmits the first processed pixels to a back-end circuit or transmits the first processed pixels to the second buffer circuit. When the assigning circuit transmits the first processed pixels to the second buffer circuit, the first selector circuit transm its the first processed pixels to the processor circuit, the processor circuit performs a second filtering process on the first processed pixels to generate second processed pixels, and the assigning circuit transmits the second processed pixels to the back-end circuit.

Abstract: A chimeric antigen receptor, includes an extracellular domain, a transmembrane domain, and an intracellular domain, which are connected in sequence, where the extracellular domain includes an antigen recognition region and a hinge region, and one end of the intracellular domain which is connected to the transmembrane domain is connected to a CD3? intracellular region. The chimeric antigen receptor can further improve the treatment effect of B-cell leukemia lymphoma, and reduce inflammatory cytokines generated from macrophage mononuclear cell activation by down-regulating cytokines, so that cytokine storm can be prevented in an early stage, and the risk of neurotoxicity can be reduced. The treatment effect of mesothelin high-expression solid tumors is further improved in mesothelin-positive tumor treatment, and the prevention of cytokine storm and the reduced risk of neurotoxicity can be realized at an early stage.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a workpiece including a first semiconductor fin and a second semiconductor fin penetrating from a substrate and separated by a first isolation feature, and a gate structure intersecting the first semiconductor fin and the second semiconductor fin. The method also includes removing the gate structure and portions of the first semiconductor fin, the second semiconductor fin, and the first isolation feature disposed directly under the gate structure to form a fin isolation trench, forming a dielectric layer over the workpiece to substantially fill the fin isolation trench, and planarizing the dielectric layer to form a fin isolation structure in the fin isolation trench.

Abstract: An array substrate and a display panel are disclosed. The display panel includes the array substrate. An ion injection stopper layer and an active layer of the array substrate correspond to at least part of the channel part. The ion injection stopper layer blocks ions from being injected into the channel part. Therefore, an effective channel length of oxide TFTs is reduced. A width of a channel of the oxide TFTs can be reduced without changing a width-length ratio of the oxide TFTs. As such, a size of the oxide TFTs can be reduced, and an aperture ratio of the display panel is increased.

Abstract: The invention provides DNA molecules and constructs, and their nucleotide sequences, useful for modulating gene expression in plants, and for specifying intracellular or extracellular localization of a gene product of interest. Transgenic plants, plant cells, plant parts, and seeds, comprising the DNA molecules operably linked to heterologous transcribable polynucleotides are also provided.

Abstract: A semiconductor structure includes a semiconductor substrate, a gate electrode, a first spacer, and a first contact etch stop layer (CESL). The semiconductor substrate includes a fin structure. The gate electrode is over the fin structure. The first spacer is over the fin structure and on a lateral side of the gate electrode, wherein a top surface of the first spacer is inclined towards the gate electrode. The first CESL is over the fin structure and contacting the first spacer, wherein an angle between the top surface of the first spacer and a sidewall of the first CESL is less than about 140°.

Abstract: A second-generation high temperature superconducting (HTS) strip and a preparation method thereof are provided. The second-generation HTS strip includes a superconducting strip body and a stabilizing layer arranged thereon. The stabilizing layer is a copper-graphene composite film with a total thickness of 2-30 microns on one side. The superconducting strip may be obtained by the preparation method of: (1) putting a superconducting strip body into a magnetron sputtering reaction chamber, followed by pumping to a high-level vacuum and filling with a working gas; (2) using copper and graphene as targets, and performing a sputter coating by controlling a magnetron sputtering power, to deposit the targets onto at least one surface of the superconducting strip body.

Abstract: A protective film thickness measuring method includes a step of applying light to a top surface of a wafer in a state in which no protective film is formed and measuring a first reflection intensity of the light reflected from the top surface, a step of forming the protective film including a light absorbing material, a step of irradiating the protective film with exciting light of a wavelength at which the light absorbing material fluoresces and measuring a second reflection intensity including fluorescence of the protective film and the light reflected from the top surface, and a step of excluding reflection intensity of patterns formed on the top surface, by subtracting the measured first reflection intensity from the measured second reflection intensity, and calculating fluorescence intensity of the protective film.