Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first microelectronic elements on a first temporary substrate; and replacing at least one defective microelectronic element of the first microelectronic elements with at least one second microelectronic element. The first microelectronic elements and at least one second microelectronic element are distributed on the first temporary substrate. The first microelectronic elements and at least one second microelectronic element have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first microelectronic elements and at least one second microelectronic element. A semiconductor structure and a display panel are also provided.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a workpiece including a first semiconductor fin and a second semiconductor fin penetrating from a substrate and separated by a first isolation feature, and a gate structure intersecting the first semiconductor fin and the second semiconductor fin. The method also includes removing the gate structure and portions of the first semiconductor fin, the second semiconductor fin, and the first isolation feature disposed directly under the gate structure to form a fin isolation trench, forming a dielectric layer over the workpiece to substantially fill the fin isolation trench, and planarizing the dielectric layer to form a fin isolation structure in the fin isolation trench.

Abstract: An array substrate and a display panel are disclosed. The display panel includes the array substrate. An ion injection stopper layer and an active layer of the array substrate correspond to at least part of the channel part. The ion injection stopper layer blocks ions from being injected into the channel part. Therefore, an effective channel length of oxide TFTs is reduced. A width of a channel of the oxide TFTs can be reduced without changing a width-length ratio of the oxide TFTs. As such, a size of the oxide TFTs can be reduced, and an aperture ratio of the display panel is increased.

Abstract: An image processing circuit includes a first buffer circuit, a first selector circuit, a processor circuit, a second buffer circuit, and an assigning circuit. The first buffer circuit receives pixels in a sliding window of an image. The first selector circuit outputs the pixels according to a mode signal. The processor circuit performs a first filtering process on the pixels to generate first processed pixels. The assigning circuit transmits the first processed pixels to a back-end circuit or transmits the first processed pixels to the second buffer circuit. When the assigning circuit transmits the first processed pixels to the second buffer circuit, the first selector circuit transm its the first processed pixels to the processor circuit, the processor circuit performs a second filtering process on the first processed pixels to generate second processed pixels, and the assigning circuit transmits the second processed pixels to the back-end circuit.

Abstract: The invention provides DNA molecules and constructs, and their nucleotide sequences, useful for modulating gene expression in plants, and for specifying intracellular or extracellular localization of a gene product of interest. Transgenic plants, plant cells, plant parts, and seeds, comprising the DNA molecules operably linked to heterologous transcribable polynucleotides are also provided.

Abstract: A chimeric antigen receptor, includes an extracellular domain, a transmembrane domain, and an intracellular domain, which are connected in sequence, where the extracellular domain includes an antigen recognition region and a hinge region, and one end of the intracellular domain which is connected to the transmembrane domain is connected to a CD3? intracellular region. The chimeric antigen receptor can further improve the treatment effect of B-cell leukemia lymphoma, and reduce inflammatory cytokines generated from macrophage mononuclear cell activation by down-regulating cytokines, so that cytokine storm can be prevented in an early stage, and the risk of neurotoxicity can be reduced. The treatment effect of mesothelin high-expression solid tumors is further improved in mesothelin-positive tumor treatment, and the prevention of cytokine storm and the reduced risk of neurotoxicity can be realized at an early stage.

Abstract: A semiconductor structure includes a semiconductor substrate, a gate electrode, a first spacer, and a first contact etch stop layer (CESL). The semiconductor substrate includes a fin structure. The gate electrode is over the fin structure. The first spacer is over the fin structure and on a lateral side of the gate electrode, wherein a top surface of the first spacer is inclined towards the gate electrode. The first CESL is over the fin structure and contacting the first spacer, wherein an angle between the top surface of the first spacer and a sidewall of the first CESL is less than about 140°.

Abstract: A second-generation high temperature superconducting (HTS) strip and a preparation method thereof are provided. The second-generation HTS strip includes a superconducting strip body and a stabilizing layer arranged thereon. The stabilizing layer is a copper-graphene composite film with a total thickness of 2-30 microns on one side. The superconducting strip may be obtained by the preparation method of: (1) putting a superconducting strip body into a magnetron sputtering reaction chamber, followed by pumping to a high-level vacuum and filling with a working gas; (2) using copper and graphene as targets, and performing a sputter coating by controlling a magnetron sputtering power, to deposit the targets onto at least one surface of the superconducting strip body.

Abstract: A protective film thickness measuring method includes a step of applying light to a top surface of a wafer in a state in which no protective film is formed and measuring a first reflection intensity of the light reflected from the top surface, a step of forming the protective film including a light absorbing material, a step of irradiating the protective film with exciting light of a wavelength at which the light absorbing material fluoresces and measuring a second reflection intensity including fluorescence of the protective film and the light reflected from the top surface, and a step of excluding reflection intensity of patterns formed on the top surface, by subtracting the measured first reflection intensity from the measured second reflection intensity, and calculating fluorescence intensity of the protective film.

Abstract: An operational amplifier includes a first amplifying unit, a second amplifying unit, a current source, a first compensation capacitor, and a second compensation capacitor. The first amplifying unit includes a first input transistor, a second input transistor, a third input transistor, and a fourth input transistor. The second amplifying unit includes a fifth input transistor, a sixth input transistor, a seventh input transistor, and an eighth input transistor. One end of the first compensation capacitor is coupled to a drain of the seventh input transistor, and the other end of the first compensation capacitor is coupled to a gate of the eighth input transistor. One end of the second compensation capacitor is coupled to a drain of the eighth input transistor, and the other end of the second compensation capacitor is coupled to a gate of the seventh input transistor.

Abstract: Aspects of the invention disclose an external and an add-on anamorphic lens, which comprises a focus group and an anamorphic group disposed in sequence from an object side to an image side along the optical axis. The focus group comprises a first lens and a second lens. The first lens and the second lens are spherical lenses. The anamorphic group includes a third lens, a fourth lens, and a fifth lens. These lenses are cylindrical lenses. The position of the first lens is adjustable and therefore solve the problem of requiring secondary focusing of the prior art.

Abstract: A transmitter device adapted to be coupled to an image providing device and a receiver device includes first and second conversion units, a wireless module, and a processing unit. The first conversion unit and the second conversion unit are configured to be coupled to the image providing device through an HDMI transmission cable and a Type-C transmission cable, respectively, so as to respectively receive a first video and audio stream and a second video and audio stream provided by the image providing device. The wireless module is connected to the receiver device through wireless communication. The processing unit preferentially selects the first conversion unit to receive a first video and audio signal output by converting the first video and audio stream by the first conversion unit and transmits the first video and audio signal to the receiver device through the wireless module.

Abstract: Disclosed are a semiconductor package and a manufacturing method of a semiconductor package. In one embodiment, the semiconductor package includes an interposer substrate, a plurality of semiconductor dies, a first encapsulant, at least one heat dissipation element and a second encapsulant. The plurality of semiconductor dies are disposed on the interposer substrate. The first encapsulant is disposed on the interposer substrate and surrounds the plurality of semiconductor dies. The at least one heat dissipation element is disposed on the plurality of semiconductor dies. The second encapsulant is disposed on the first encapsulant and surrounds the at least one heat dissipation element.

Abstract: A method of forming an SSZ-13 zeolite in a hydrothermal synthesis yields an SSZ-13 zeolite that exhibits a silica to alumina (SiO2:Al2O3) molar ratio (SAR) that is less than 16:1; has a morphology that includes one or more of cubic, spheroidal, or rhombic particles with a crystal size that is in the range of about 0.1 micrometer (?m) to 10 ?m. This SSZ-13 also exhibits a Brönsted acidity that is in the range of 2.0 mmol/g to 3.4 mmol/g as measured by ammonia temperature programmed desorption. A catalyst formed by substituting a metal into the framework of the zeolite provides for low temperature light-off of the NOx conversion reactions, while maintaining substantial performance at higher temperatures demonstrating hydrothermal stability.

Abstract: A method, system, and computer program product to manage a network comprising a plurality of interconnected components are described. The method includes obtaining a set of all the components that are part of the network over time, and identifying one or more repeating patterns of components among the set of all the components as corresponding lower-level definitions to generate a hierarchical set of all the components. The method also includes obtaining time-varying information regarding topology and operational values within the network, and creating a representation of the network at a set of times based on the hierarchical set of all the components and the time-varying information.

Abstract: A method for expanding functions of a conference system includes providing a first circuit board and a second circuit board disposed in the receiver, receiving a first wireless packet transmitted from the first transmitter merely through a second communication module of the second circuit board, controlling the second communication module for performing an unpacking process of the first wireless packet by a second processor of the second circuit board to generate first compressed media data, generating a first command signal by the second processor of the second circuit board for controlling a first processor of the first circuit board to receive the first compressed media data through a data channel, and decompressing the first compressed media data by the first processor for acquiring first media contents of the first transmitter.

Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

Abstract: Methods, apparatuses, and systems for establishing various network configurations within a gas detection system. The method includes initializing, by a computing device associated with a gateway, a root node of a tree network, monitoring for a beacon request broadcast, wherein the beacon request broadcast is detected by the computing device from a given one of the one or more broadcasting devices, the given broadcasting device switching over from a parallel network configuration to join the tree network, determining available capability to support a connection with the broadcasting device, generating a beacon response based on the determination of available capability, transmitting the beacon response to the broadcasting device, establishing the broadcasting device as a child node device based upon a receipt of a joining request, and transmitting a join confirmation to the broadcasting device based on the establishment of the broadcasting device as a child node device.