Abstract: A test method and system of testing a semiconductor device is provided. The method includes placing a packaged semiconductor device on a tester and engaging a thermal management component with an upper surface of the packaged semiconductor device. The packaged semiconductor device is tested using the tester, and during the testing a first thermal condition is delivered to a first region of the thermal management component while delivering a second thermal condition is delivered to a second region of the thermal management component. The first thermal condition is different than the second thermal condition.

Abstract: The present disclosure describes a system with multi-zone impingement cooling of a semiconductor device. The system includes a first die and a second die on a substrate, a heat transfer structure, and a controller. The heat transfer structure includes a first compartment disposed over the first die, a second compartment disposed over the second die and separate from the first compartment, a first inlet pipe connected to the first compartment and configured to supply a first liquid coolant to the first compartment, and a second inlet pipe connected to the second compartment and configured to supply a second liquid coolant to the second compartment. The controller is configured to control a first flow rate of the first liquid coolant based on a temperature of the first die and a second flow rate of the second liquid coolant based on a temperature of the second die.

Abstract: One aspect of the present disclosure pertains to an integrated circuit (IC) structure. The IC structure includes a die and an integrated heat sink structure disposed over the die. In some embodiments, the integrated heat sink structure includes a first closed-loop microchannel structure adjacent to the die and a second closed-loop microchannel structure disposed over the first closed-loop microchannel structure. In an example, the second closed-loop microchannel structure is disposed further away from the die that the first closed-loop microchannel structure. In some implementations, a plurality of microchannels and a micromixer chamber collectively provide the first and second closed-loop microchannel structures.

Abstract: The present disclosure provides an integrated circuit (IC) structure that includes an IC packaging structure having an IC chip; and a thermoelectric self-cooling device (TESCD) integrated with the IC packaging structure. The TESCD further includes a thermoelectric cooling (TEC) device having a plurality of TEC units configured in an array and electrically connected to provide cooling effect to the IC packaging structure, and a liquid cooling module having a cooling liquid driving device and a generator coupled with the cooling liquid driving device to collectively generate an electrical power supplied to the TEC device with self-cooling function to the IC packaging structure.

Abstract: A method for forming a device substrate is provided. The method includes forming a device layer on a semiconductor substrate, forming an interconnect structure over the device layer, and forming a redistribution layer over the interconnect structure. The interconnect structure includes stacked levels of dielectric layers and conductive connectors in the respective dielectric layers. The conductive connectors are divided into groups. The conductive connectors in a first group are connected to one another. The redistribution layer includes a first conductive pad connected to the first group of conductive connectors. The method further includes forming a polymer layer over the redistribution layer, and patterning the polymer layer to form a first opening partially exposing a first conductive pad. In a plan view, a dimension of the first group of conductive connectors is less than a dimension of the first opening.

Abstract: A liquid cooling system includes a thermoelectric cooler (TEC) between a radiator plate and a radiator, and a thermoelectric generator (TEG) at a location where the TEG is driven by heat from a chip package. The chip package is cooled by a cold plate of the liquid cooling system and the TEC is controlled by the TEG. The TEG may be between the chip package and the cold plate or elsewhere in or adjacent to the chip package. The TEG may control the TEC through a relay. The TEG automatically activates the TEC when the chip package is under peak load.

Abstract: A method and system for control of a battery thermal management (BTM) of an electric drive bulldozer includes: obtaining a load segment at a current moment “t” in a load spectrum; predicting a load segment at a next moment “t+1” in the load spectrum using a Markov chain model; carrying out a weighting calculation of the obtained and predicted load segments; calculating motor speed, motor torque, and a state of charge (SOC) of a battery based on the calculated weight; and taking the calculated motor speed, motor torque, and SOC, and other parameters as input quantities to an electric compressor rotating speed prediction model so as to obtain a desired speed of the electric compressor and further obtain a method for control of the BTM of the electric drive bulldozer.

Abstract: A package structure includes a high-power package attached to a substrate; a first low-power package attached to the substrate; a first heat dissipation device attached to the first low-power package; a liquid cooling system attached to the high-power package; and a thermoelectric system sandwiched between the high-power package and the liquid cooling system, wherein the thermoelectric system is electrically connected to the first heat dissipation device, wherein the thermoelectric system provides the first heat dissipation device with electrical power during operation of the high-power package.

Abstract: An integrated circuit package and the method of forming the same are provided. An integrated circuit package may include a first die having a first substrate over a package substrate and a lid. A first channel may extend through the first substrate from a first sidewall of the first die to a second sidewall of the first die. The lid may include a top portion over the first die and a first bottom portion extending along the first sidewall of the first die. The first bottom portion may include a second channel connected to the first channel.

Abstract: A display panel includes an active area; a fanout region; and a bonding region located on one side of the fanout region away from the active area. A driver chip is disposed in the bonding region. The driver chip includes a first side edge adjacent to the fanout region, a second side edge opposite to the first side edge, and two third side edges. The driver chip includes a plurality of output terminals disposed close to the first side edge. The display panel includes: a plurality of fanout lines located in the fanout region; and a plurality of gull-wing lines located in the bonding region. Part of the fanout lines extend from the fanout region to a region where the first side edge is located, and are electrically connected to the output terminals. Another part of the fanout lines are electrically connected to the output terminals via the gull-wing lines.

Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor substrate, a lower interconnect structure, an upper interconnect structure, a conductive pad, and a pillar bump. The lower interconnect structure is formed over the semiconductor substrate. The lower interconnect structure includes a plurality of lower dielectric layers. The lower interconnect structure also includes a plurality of lower metal lines and a plurality of lower metal vias formed in the lower dielectric layers. The upper interconnect structure is formed over the lower interconnect structure. The conductive pad is formed over the upper interconnect structure. The pillar bump structure is in direct contact with the conductive pad. The pillar bump structure includes at least two protrusions protruding toward the conductive pad and laterally separated from each other.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.

Abstract: Provided are devices and methods for forming devices. A device includes a workpiece; a thermal interface material (TIM) disposed over the workpiece; and a lid disposed over the workpiece, wherein the lid has an underside formed with a trench, and wherein a vertically extending portion of the TIM extends into the trench and a base portion of the TIM is located outside of the trench.

Abstract: A method of manufacturing a device includes bonding a first die and a second die to a first side of a substrate, forming a stress buffer structure over the first die and the second die, where the stress buffer structure includes a first portion of a first via extending through a first insulating layer, a second portion of the first via extending through a second insulating layer, and a third portion of the first via extending through a third insulating layer, where the second portion of the first via is disposed between the first portion of the first via and the third portion of the first via, and where a diameter of the second portion of the first via is smaller than diameters of the first portion of the first via and the third portion of the first via, and depositing a metal layer over the stress buffer structure.

Abstract: The present disclosure provides a driving module and a display device. The driving module includes a serial-parallel conversion circuit and a data providing circuit, the serial-parallel conversion circuit is configured to convert a serial input signal into a parallel output signal and generate a transmission control signal and a common electrode voltage signal in accordance with mode indication information carried by the parallel output signal, and the parallel output signal carries the mode indication information and input display data; and the data providing circuit is configured to convert the input display data into output display data and transmit the output display data to a corresponding data line under the control of the transmission control signal. According to the embodiments of the present disclosure, it is able to achieve display through relying on serial input signals and other signals provided by a system without a display chip.

Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.

Abstract: The present disclosure provides a gate driving circuit and a display panel. The display panel includes a display area and a peripheral area surrounding the display area. At least one gate driving circuit is arranged in the peripheral area. The at least one gate driving circuit includes a plurality of shift register units cascaded in sequence. The plurality of shift register units include first shift register units and second shift register units. The first shift register units and the second shift register units are spaced apart from each other. The number of transistors in the first shift register units is smaller than the number of transistors in the second shift register units.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.

Abstract: An vehicle anti-theft method and a vehicle anti-theft system is disclosed. The vehicle anti-theft method is implemented by at least a vehicle electronic anti-theft system, a chassis electronic control unit and an electronic parking brake. The method includes (i) generating, by the chassis electronic control unit, a random number, and sending the random number to the vehicle electronic anti-theft system, (ii) between the chassis electronic control unit and the vehicle electronic anti-theft system, based on the random number and PIN and secret key parameters initially configured in the chassis electronic control unit and the vehicle electronic anti-theft system, performing an anti-theft authentication, and obtaining an anti-theft authentication result, and (iii) based on the anti-theft authentication result, controlling, by the electronic parking brake, whether to unlock wheel calipers.