Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.

Abstract: An IC driver includes a cascode arrangement of first-type transistors coupled in series with a cascode arrangement of second-type transistors different from the first-type transistors. Each cascode arrangement includes an active area extending in a first direction, gate structures extending perpendicular to the first direction and overlying the active area at locations corresponding to the transistors of the cascode arrangement, first through fourth metal segments extending in the first direction in a first metal layer of the IC, first and second vias electrically coupling respective first and second gate structures to the first and second metal segments, a third via electrically coupling a source terminal of the cascode arrangement to the third metal segment, and a fourth via electrically coupling a drain terminal of the cascode arrangement to the fourth metal segment. The third and fourth metal segments are aligned along the first direction.

Abstract: A cantilever probe module includes a plurality of first probes and a plurality of second probes. Each of the first probes includes a first arm segment, a first main segment, and a first testing segment, the latter two of which are respectively connected to two ends of the first arm segment. Each of the second probes includes a second arm segment, an extending segment and a second testing segment both respectively connected to two ends of the second arm segment, and a second main segment that is connected to the extending segment. A height of the extending segment is 5% to 50% of a height of the second main segment. When the first main segments of the first probes and the second main segments of the second probes are staggeredly fixed onto a substrate, the first testing segments and the second testing segments are arranged in one row.

Abstract: A solder receiving probe includes an arm segment, a main segment located at one side of the arm segment, and a testing segment connected to another side of the arm segment. The main segment has a soldering end portion and an extending end portion respectively located at two opposite sides thereof along a predetermined direction. The main segment has a plurality of solder receiving holes that are arranged along a top edge of the soldering end portion and that are arranged in one row along an extending direction perpendicular to the predetermined direction. Any two of the solder receiving holes adjacent to each other are provided with one inner supporting arm therebetween. Each of the solder receiving holes can receive a solder, so that the solder does not climb across the solder receiving holes of the one row along the predetermined direction.

Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.

Abstract: A light scattering probe includes an arm segment, a main segment located at one side of the arm segment, and a testing segment connected to another side of the arm segment. The main segment has a soldering end portion and an extending end portion respectively located at two opposite sides thereof along a predetermined direction. The testing segment has an upright shape along the predetermined direction and includes a pinpoint portion and an upright portion that connects the pinpoint portion and the arm segment. The upright portion has a roughened surface arranged on an entirety of an outer surface thereof. The roughened surface has an arithmetic average roughness (Ra) within a range from 0.1 ?m to 1 ?m. Through the roughened surface, the testing segment only forms an observation point at the pinpoint portion in an observation process of a detection apparatus.

Abstract: A light absorption probe includes an arm segment, a main segment located at one side of the arm segment, a testing segment connected to another side of the arm segment, and a light absorption coating layer. The main segment has a soldering end portion and an extending end portion respectively located at two opposite sides thereof along a predetermined direction. The testing segment has an upright shape along the predetermined direction and includes a pinpoint portion and an upright portion that connects the pinpoint portion and the arm segment. The light absorption coating layer covers the upright portion, and the pinpoint portion is exposed from the light absorption coating layer. Through the light absorption coating layer, the testing segment only forms an observation point at the pinpoint portion in an observation process of a detection apparatus.

Abstract: A micro electro mechanical system (MEMS) probe includes an arm segment, a main segment, and a testing segment. The main segment is arranged at one side of the arm segment, the main segment defines a layout region arranged inside of an outer contour thereof, and the main segment has a soldering end portion and an extending end portion respectively arranged at two opposite sides of the distribution region along a predetermined direction. The testing segment has an upright shape along the predetermined direction and is connected to another side of the arm segment. The layout region has a plurality of thru-holes that occupy 3% to 70% of a region surroundingly defined by the outer contour. The layout region is spaced apart from the outer contour by a layout spacing that is less than or equal to an inner diameter of any one of the thru-holes.

Abstract: A climb-restricting probe includes an arm segment, a main segment located at one side of the arm segment, a testing segment connected to another side of the arm segment, and a climb-restricting ring. The main segment has a soldering end portion and an extending end portion respectively located at two opposite sides thereof along a predetermined direction. The testing segment has an upright shape along the predetermined direction. The climb-restricting ring surrounds the main segment along a top edge of the soldering end portion and protrudes from an outer surface of the main segment. The climb-restricting ring has a restriction height along the predetermined direction. The restriction height is within a range from 3 ?m to 50 ?m. The climb-restricting ring can block a solder from climbing past the climb-restricting ring along the predetermined direction.

Abstract: A vertical probe card having different probes is provided, and includes a first guiding board unit, a second guiding board unit, and a plurality of fence-like probes passing through the first and the second guiding board units. Each of the fence-like probes has a probe length within a range from 5 mm to 8 mm, and includes a fence-like segment, a connection segment, and a testing segment. The fence-like segment includes a penetrating slot having a length greater than 65% of the probe length. The fence-like segment includes two arms respectively arranged at two opposite sides of the penetrating slot and spaced apart from each other by an adjustment distance within a range from 10 ?m to 120 ?m. The fence-like probes include a first probe and a second probe, which have a same contact force and are configured to respectively meet different electrical transmission requirements.

Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.

Abstract: An adjustment method of screen brightness comprises the following steps. Step (a): obtaining a relationship between a brightness and refresh rate of the screen. Step (b): adjusting the screen to a highest refresh rate and displaying an image at a first brightness. Step (c): decreasing the first brightness by a unit brightness value and variably displaying the image between a first refresh rate and a second refresh rate. Step (d): determining whether the image does not flicker; if not, repeating step (c). Step (e): calculating a first brightness difference between a decreased brightness of the screen and a brightness corresponding to a lowest refresh rate when the image does not flicker. Step (f): determining whether the first brightness difference is less than a screen flicker threshold; if yes, decreasing the first brightness corresponding to the highest refresh rate to obtain an adjusted brightness corresponding to the highest refresh rate.

Abstract: In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.

Abstract: An improved structure of a Universal Serial Bus (USB) connector is provided. The improved structure of the USB connector includes: a middle partition, including a base part and a tongue part extending from the base part; an upper row of terminals disposed above the base part, wherein the upper row of terminals have a first contact part having a first width and extending to the tongue part; and a lower row of terminals disposed under the base part, wherein the lower row of terminals have a second contact part having a second width and extending to the tongue part, wherein the tongue part has a third width, and the first width, second width and third width have the same distance.

Abstract: A wireless management system includes a controller and energy storage units. Each of the energy storage units includes an energy storage device and a node substrate. The wireless management system is configured to select a first node substrate from the node substrates based on a signal strength of each of first request signals to join a local network by the controller. The wireless management system is further configured to select a second node substrate from the node substrates based on the signal strength of each of second request signals to join the local network by the first node substrate. The wireless management system is further configured to assign a serial number corresponds to each of the energy storage units based on the local network by the controller.

Abstract: A package structure includes a supporting base, conductive pillars, a first semiconductor die, a second semiconductor die, a first adhesive material, a second adhesive material and an isolation structure. The conductive pillars are disposed in the supporting base, and protruding out from a top surface of the supporting base. The second semiconductor die is adjacent to the first semiconductor die, wherein the first and second semiconductor dies are disposed on the supporting base and electrically connected to the conductive pillars. The first adhesive material is disposed in between the first semiconductor die and the top surface of the supporting base, and partially covering the conductive pillars. The second adhesive material is disposed in between the second semiconductor die and the top surface of the supporting base, and partially covering the conductive pillars. The isolation structure prevents a bleeding of the first and second adhesive material to an adjacent semiconductor die.

Abstract: A foldable device may include a foldable layer and a hinge mechanism. The hinge mechanism may include at least one synchronizing module, at least one torsion module, and a cover module. The at least one synchronizing module may include a synchronizing gear assembly including a first linking gear in meshed engagement with a first rotating link, a second linking gear in meshed engagement with a second rotating link, and at least one intermediate gear in meshed engagement with the first linking gear and the second linking gear. The first rotating link may be coupled to a first housing of a computing device and the second rotating link may be coupled to a second housing of the computing device. The meshed engagement of the first and second rotating links may provide of synchronized, symmetric movement of the first and second housings about a central axis of the computing device.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: The method comprising determining a set of coordinates each for two or more appearances of a target subject within a sequence of images, the set of coordinates of the two or more appearances of the target subject defining a first path; determining a set of coordinates each for two or more appearances of a related subject within a sequence of images, the related subject relating to the target subject, the set of coordinates of the two or more appearances of the related subject defining a second path; determining one or more minimum distances between the first path and the second path so as to determine at least a region of interest; determining a timestamp of a first appearance and a timestamp of a last appearance of the target subject; and determining a timestamp of a first appearance and a timestamp of a last appearance of the related subject.

Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.