Abstract: Methods and devices that include forming a first epitaxial region and a second epitaxial region above the first epitaxial region. An opening may be formed extending from the first region to the second region. And a liner layer is deposited on a sidewall and a bottom of the opening. A plasma treatment is performed on the liner layer, which can form a conditioned or passivated region of the first epitaxial region that may be maintained during the growth of additional epitaxial material on the second epitaxial region.

Abstract: A semiconductor device includes a substrate, a routing structure, a device layer and a bonding layer. The routing structure is disposed over the substrate, and includes a plurality of dielectric layer and a plurality of conductive features. The device layer is disposed over the routing structure. The bonding layer is disposed between the substrate and the routing structure, wherein the bonding layer includes a plurality of microchannels.

Abstract: Provided are a semiconductor structure including high kappa (high-K) material for source/drain (S/D) and/or thermal heat spreader and a method of forming the same. The semiconductor device includes a substrate, a plurality of channel layers stacked over the substrate, a gate structure wrapping the plurality of channel layers, and source/drain (S/D) regions disposed over the substrate at opposite sides of the gate structure and connecting the plurality of channel layers. A material of the S/D regions includes a high thermal conductivity material with a single crystal structure, such as boron arsenide (BAs) with a thermal conductivity greater than 1000 W/mK. In this case, the high thermal conductivity material can efficiently dissipate the heat generated by the semiconductor structure to enhance the yield and the reliability of the semiconductor structure.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.

Abstract: High resolution 3D thermal imaging can be obtained by using enhanced non-destructive heat transducer designs. A thermal property measurement method includes providing a sample for thermal property measurement, and bonding a transducer layer on the sample through a temporary bonding layer. Thermal measurement processes are performed along the X-Y, X-Z and Y-Z planes of the sample, wherein the X-Y plane is parallel to a top surface of the sample, and the X-Z plane and Y-Z plane are perpendicular to the top surface of the sample. Each thermal measurement processes include heating a designated region of the sample covered with the transducer layer using a pump laser, and using a probe laser for generating a reflectance signal of the sample, and determining a thermal conductivity in the designated region of the sample from the reflectance signal. Furthermore, the transducer layer is removed along with the temporary bonding layer from the sample.

Abstract: An electronic device includes a substrate and a first light shielding layer disposed on the substrate. The first light shielding layer includes a first light shielding pattern extending along a direction and a second light shielding pattern adjacent to the first light shielding pattern and extending along the direction. In a cross-sectional view of the electronic device, a first opening is included between the first light shielding pattern and the second light shielding pattern, the first light shielding pattern has a first width, the first opening has a second width, and a ratio of the first width to the second width range from 0.5 to 2.

Abstract: The disclosure provides a display device that includes a camera region and a display region adjacent to the camera region. The camera region includes a first region and a second region which allows a light beam to pass through. The first region includes a plurality of first display pixels. The display region includes a plurality of second display pixels. An area of each of the plurality of first display pixels is greater than an area of each of the plurality of second display pixels. The first region is adjacent to the second region. The first region includes a plurality of edges, and the second region is adjacent to two of the plurality of edges.

Abstract: A manufacturing method of a heat dissipation layer is provided. A first carrier substrate and a second carrier substrate creating a first confined space therebetween are provided. A first seed layer is formed on the first carrier substrate and a second seed layer is formed on the second carrier substrate. A first heat dissipation layer is formed from the first seed layer and the second seed layer in the first confined space. The second carrier substrate is removed from the first heat dissipation layer.

Abstract: A semiconductor device having a low-k isolation structure and a method for forming the same are provided. The semiconductor device includes channel structures, laterally extending on a substrate; gate structures, intersecting and covering the channel structures; and a channel isolation structure, laterally penetrating through at least one of the channel structures, and extending between separate sections of one of the gate structures along an extending direction of the one of the gate structures. A low-k dielectric material in the channel isolation structure comprises boron nitride.

Abstract: A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.

Abstract: A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed, a contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.

Abstract: A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure having a first surface and a second surface opposite to the first surface, a high-power die over the substrate structure, a lower-power die over the high-power die, a first interposer between the first surface of the substrate structure and the high-power die, and a second interposer between the high-power die and the lower-power die. The substrate structure includes a thermal enhancement portion located under the high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure. A substrate structure of the 3D integrated circuit package is also provided.

Abstract: An electronic device includes a substrate, a driving element, a first insulating layer, a pixel electrode layer, and a common electrode layer. The driving element is disposed on the substrate. The first insulating layer is disposed on the driving element. The pixel electrode layer is disposed on the first insulating layer. The first insulating layer comprises a hole, and the pixel electrode layer is electrically connected to the driving element through the hole. The common electrode layer is disposed on the pixel electrode layer. The common electrode layer comprises a slit, and the slit has an edge, and the edge is disposed in the hole.

Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

Abstract: The present disclosure provides a method that includes providing a semiconductor structure having a bottom channel region and a top channel region over the bottom channel region; forming a gate dielectric layer over and wrapping around top channels in the top channel region; performing a radical treatment on the dielectric layer in a supercritical fluid; and forming a metal gate electrode on the dielectric layer.

Abstract: The present disclosure provides a method that includes providing a semiconductor structure having a bottom channel region and a top channel region over the bottom channel region; forming a gate dielectric layer over and wrapping around top channels in the top channel region; performing a radical treatment on the dielectric layer in a supercritical fluid; and forming a metal gate electrode on the dielectric layer.

Abstract: Gate dielectric materials and related methods for stacked device structures such as a complementary field-effect transistor (CFET) are disclosed herein. An exemplary method includes forming a two-dimensional (2D) dielectric material over a semiconductor channel layer. In some embodiments, the method further includes depositing a gate dielectric layer over the 2D dielectric material. In some examples, the method further includes forming a metal gate electrode over the gate dielectric layer. In various embodiments, a dipole is formed substantially within the 2D dielectric material, where the dipole is configured to modulate a threshold voltage (Vt) of the semiconductor device.

Abstract: Methods for forming a stacked transistor device including depositing a dummy material such as by spin-on deposition to process a first transistor differently than a second transistor of the stacked transistor device. Multi-Vt patterning, where different transistors in a stacked device can have different threshold voltages (Vt) can be implemented by depositing a dummy material before patterning to selectively control the Vt of each transistor without affecting the others. In top-bottom FET stacks, by depositing a dummy material, the process can be optimized to ensure that each transistor in the stack is formed with the desired characteristics.

Abstract: A method includes forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A first dipole film and a second dipole film are formed on the first gate dielectric and the second gate dielectric, respectively. The Dipole dopants in the first dipole film and the second dipole film are driven into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are then removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form first transistor and a second transistor, respectively.