Patents by Inventor Wei Yen

Wei Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250053384
    Abstract: A method for multiple executable binaries with static links is provided. The method includes a fixed binary generated from non-modified source program file has symbols of functions and variables with fixed addresses; a first modifiable binary generated from modified source program files has symbols of functions and variables with changed addresses; and a first reference table contains the symbols of functions and variables of the first modifiable binary which are referred by the fixed binary; wherein the first modifiable binary refers to the symbols of the fixed binary directly, and the fixed binary refers to the symbols of functions and the variables of the first modifiable binary through the first reference table at runtime.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Inventors: Wei-Chun KAO, Hsien-Ming TSAI, Jing-Yen HUANG, Ming-Chun CHENG
  • Publication number: 20250054849
    Abstract: A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.
    Type: Application
    Filed: July 22, 2024
    Publication date: February 13, 2025
    Inventors: Wei-Luen SUEN, Po-Jung CHEN, Chia-Ming CHENG, Po-Shen LIN, Jiun-Yen LAI, Tsang-Yu LIU, Shu-Ming CHANG
  • Publication number: 20250056911
    Abstract: A chip package includes a semiconductor substrate, a light-transmissive plate, a bonding layer, and a light-shielding layer. The bonding layer is located between the semiconductor substrate and the light-transmissive plate. The semiconductor substrate, the bonding layer, and the light-transmissive plate jointly define a sidewall including a first region and a second region. The first region extends from the semiconductor substrate to the light-transmissive plate, and is recessed relative to the second region. The light-shielding layer covers the sidewall and includes an extending portion, a wide portion, and a narrow portion. The extending portion is located on a surface of the semiconductor substrate facing away from the bonding layer. The wide portion is located on the first region of the sidewall. The narrow portion is located on the second region of the sidewall.
    Type: Application
    Filed: June 21, 2024
    Publication date: February 13, 2025
    Inventors: Wei-Luen SUEN, Chien Wei CHANG, Zi-Yu LIAO, Jiun-Yen LAI, Tsang Yu LIU
  • Patent number: 12223330
    Abstract: A BIOS setup environment configuration modification audit system includes a BIOS device that is included in a computing device and that is coupled to a component device in the computing device. The BIOS device enters a BIOS setup environment for the computing device and, while in the BIOS setup environment, detects component device configuration modification(s) to a configuration of the component device.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: February 11, 2025
    Assignee: Dell Products L.P.
    Inventors: Wei Liu, Chih-Chao Liu, Gin Yen Yang
  • Patent number: 12217647
    Abstract: An electronic device including a plurality of pixels and a driving element is provided. Each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The driving element drives each first sub-pixel of the plurality of pixels.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: February 4, 2025
    Assignee: Innolux Corporation
    Inventors: Chia-Hao Tsai, You-Cheng Lu, Yi-Shiuan Cherng, Wei-Yen Chiu
  • Patent number: 12218225
    Abstract: The present disclosure provides a method that includes providing a semiconductor structure having a bottom channel region and a top channel region over the bottom channel region; forming a gate dielectric layer over and wrapping around top channels in the top channel region; performing a radical treatment on the dielectric layer in a supercritical fluid; and forming a metal gate electrode on the dielectric layer.
    Type: Grant
    Filed: December 20, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ming Lin, Kenichi Sano, Wei-Yen Woon, Szuya Liao
  • Publication number: 20250038071
    Abstract: An integrated circuit is provided, including a first transistor of a first conductivity type comprising first and second active regions, a second transistor of a second conductivity type comprising third and fourth active regions and arranged under the first transistor along a first direction, a first gate structure extending in the first direction and shared by the first and second transistors, an isolation layer sandwiched between the first and second transistors and extending along a second direction to pass through the first gate structure, and a connection layer surrounded by the isolation layer and extending along the second direction to pass through the first gate structure. The isolation layer has a first surface contacting the first and second active regions and a second surface contacting the third and fourth active regions. The connection layer comprises first and second portions are electrically coupled to the first and fourth active regions.
    Type: Application
    Filed: July 24, 2023
    Publication date: January 30, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng TZENG, Shih-Wei PENG, Chun-Yen LIN, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Publication number: 20250037425
    Abstract: A method for diagnosing a reason of a malfunction is provided. The method includes: receiving a signal to be diagnosed; decomposing the signal to be diagnosed into a plurality of sub-signals; transforming each of the plurality of sub-signals into a corresponding grayscale image; and inputting the corresponding grayscale images to a neural network model, and outputting a malfunction reason classification result through the neural network model. Accordingly, the method can be used for diagnosing the reason of the malfunction and solves the problem of incapable of diagnosing the reason of the malfunction. In addition, a device and a computer-readable recording medium for diagnosing the reason of the malfunction are also provided.
    Type: Application
    Filed: October 6, 2023
    Publication date: January 30, 2025
    Inventors: WEI-JYUN TU, YU-YEN CHEN, CHIEN-CHUNG LIN
  • Publication number: 20250031413
    Abstract: Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che Chi SHIH, Jhih-Rong HUANG, Han-Yu LIN, Ku-Feng YANG, Wei-Yen WOON, Szuya LIAO
  • Patent number: 12204692
    Abstract: A touch module includes a base plate, a first magnet, a second magnet, a touch pad, a first magnetic board and a second magnetic board. The first magnet and the second magnet are installed on the base plate and separated from each other. The touch pad is located over the base plate to cover the first magnet and the second magnet. The first magnetic board and the second magnetic board are separated from each other, located under the touch pad and coupled with the touch pad. The first magnetic board is aligned with the first magnet. The second magnetic board is aligned with the second magnet. The driving circuit is electrically coupled with the first magnetic board and the second magnetic board. The first magnetic board induces a magnetic field of the first magnet. The second magnetic board induces a magnetic field of the second magnet.
    Type: Grant
    Filed: September 25, 2023
    Date of Patent: January 21, 2025
    Assignee: Primax Electronics Ltd.
    Inventors: Tse-Ping Kuan, Wei-Chiang Huang, Hung-Wei Kuo, Ying-Yen Huang, Sian-Yi Chiu
  • Patent number: 12203961
    Abstract: A vertical probe card device and a fence-like probe thereof are provided. The fence-like probe has a probe length within a range from 5 mm to 8 mm. The fence-like probe includes a fence-like segment, a connection segment, and a testing segment. The fence-like segment has an elongated shape defining a longitudinal direction, and the fence-like segment has a penetrating slot and a first protrusion. The penetrating slot is formed along the longitudinal direction and has a length greater than 65% of the probe length. The first protrusion extends from one of two long walls of the penetrating slot by a first predetermined width and is spaced apart from another one of the two long walls of the penetrating slot by a first gap. The connection segment and the testing segment are respectively connected to two end portions of the fence-like segment.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: January 21, 2025
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Wei-Jhih Su, Chao-Hui Tseng, Hao-Yen Cheng, Mei-Hui Chen
  • Publication number: 20250023223
    Abstract: An antenna module and a portable electric device are provided. The antenna module includes a flexible substrate, a first antenna circuit and a second antenna circuit. Each of an L-shaped bent portion and a U-shaped bent portion of the flexible substrate has a first end and a second end opposite to each other. The first end of the L-shaped bent portion is connected to a first main body of the flexible substrate. The first end of the U-shaped bent portion is connected to the second end of the L-shaped bent portion. The second end of the U-shaped bent portion is connected to a second main body of the flexible substrate. The first antenna circuit and the second antenna circuit are respectively disposed on the first main body and the second main portion. The portable electric device includes a casing and the antenna module disposed at a corner.
    Type: Application
    Filed: June 20, 2024
    Publication date: January 16, 2025
    Inventors: Kun Yen TU, Po-Ting CHEN, Sin-Siang WANG, Wei Ting LEE
  • Publication number: 20250014947
    Abstract: Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Inventors: Kenichi Sano, Yi-Hsiu Chen, Pinyen Lin, Wei-Yen Woon
  • Patent number: 12189252
    Abstract: An electronic device is provided. The electronic device includes a substrate, a thin-film transistor, a transparent conductive layer, a first organic layer, and a second organic layer. The thin-film transistor is disposed on the substrate and includes a drain electrode. The transparent conductive layer is disposed on the drain electrode and is electrically connected to the drain electrode. The first organic layer is disposed between the drain electrode and the transparent conductive layer. The first organic layer has a through-hole. The second organic layer is disposed in the through-hole. The electronic device has a cell gap. There is a first distance between an upper surface of the first organic layer and an upper surface of the second organic layer. The cell gap and the first distance conform to the following formula: 0<the first distance?0.8Ă—the cell gap.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: January 7, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Ming-Jou Tai, Chia-Hao Tsai, Yi-Shiuan Cherng, Wei-Yen Chiu
  • Publication number: 20250006739
    Abstract: A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurali
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Cheng-Ming Lin, Chun-I Wu, Tsung-Kai Chiu, Wei-Yen Woon, Szuya Liao
  • Publication number: 20240413039
    Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a semiconductor substrate, a high-Kappa dielectric layer disposed on the semiconductor substrate, a first plurality of nanostructures disposed over the high-Kappa dielectric layer, a middle dielectric layer disposed over the first plurality of nanostructures, a second plurality of nanostructures over the middle dielectric layer, a first gate structure wrapping around the first plurality of nanostructures, a second gate structure wrapping around the second plurality of nanostructures. The high-Kappa dielectric layer includes metal nitride, metal oxide, silicon carbide, graphene, or diamond.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 12, 2024
    Inventors: Che Chi Shih, Wei-Yen Woon, Ku-Feng Yang, Szuya Liao
  • Patent number: 12166079
    Abstract: The present disclosure describes a 2D channel FET with low contact resistance and a method for forming such a structure. The method includes depositing a dielectric layer on a semiconductor substrate, depositing a metal layer on the dielectric layer, and depositing a hard mask layer on the metal layer. The method further includes forming a gate opening by removing a portion of the hard mask layer and a portion of the metal layer. The method further includes depositing a spacer material layer on sidewalls of the gate opening and forming a channel, the channel including a TMC layer, at a bottom of the gate opening. The method further includes forming a gate structure on the channel and in the gate opening and removing the hard mask layer.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Dhanyakumar Mahaveer Sathaiya, Wei-Yen Woon
  • Publication number: 20240395812
    Abstract: A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first dielectric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ming LIN, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20240395870
    Abstract: The present disclosure describes a 2D channel FET with low contact resistance and a method for forming such a structure. The method includes depositing a dielectric layer on a semiconductor substrate, depositing a metal layer on the dielectric layer, and depositing a hard mask layer on the metal layer. The method further includes forming a gate opening by removing a portion of the hard mask layer and a portion of the metal layer. The method further includes depositing a spacer material layer on sidewalls of the gate opening and forming a channel, the channel including a TMC layer, at a bottom of the gate opening. The method further includes forming a gate structure on the channel and in the gate opening and removing the hard mask layer.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal Abhijith KHADERBAD, Sathaiya Mahaveer DHANYAKUMAR, Wei-Yen WOON
  • Publication number: 20240395627
    Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of finFETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mrunal Abhijith KHADERBAD, Wei-Yen WOON, Cheng-Ming LIN, Han-Yu LIN, Szu-Hua CHEN, Jhih-Rong HUANG, Tzer-Min SHEN