Patents by Inventor Wei Yen

Wei Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250095997
    Abstract: A method of forming a semiconductor device includes depositing a target metal layer in an opening. Depositing the target metal layer comprises performing a plurality of deposition cycles. An initial deposition cycle of the plurality of deposition cycles comprises: flowing a first precursor in the opening, flowing a second precursor in the opening after flowing the first precursor, and flowing a reactant in the opening. The first precursor attaches to upper surfaces in the opening, and the second precursor attaches to remaining surfaces in the opening. The first precursor does not react with the second precursor, and the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor.
    Type: Application
    Filed: March 11, 2024
    Publication date: March 20, 2025
    Inventors: Kai-Chieh Yang, Kuan-Kan Hu, Wei-Yen Woon, Ku-Feng Yang, Szuya Liao
  • Publication number: 20250093721
    Abstract: An electronic device is provided. The electronic device includes a substrate, a thin-film transistor, a first organic layer, a conductive layer, a second organic layer and a photoresist element. The thin-film transistor is disposed on the substrate. The first organic layer is disposed on the thin-film transistor and has a through-hole. The conductive layer is disposed on the first organic layer and electrically connected to the thin-film transistor through the through-hole. The second organic layer includes a first portion and a second portion. The first portion of the second organic layer is disposed in the through-hole, and the second portion of the second organic layer covers at least a portion of a flat portion of an upper surface of the first organic layer. The photoresist element is disposed on the second organic layer.
    Type: Application
    Filed: November 29, 2024
    Publication date: March 20, 2025
    Inventors: Ming-Jou TAI, Chia-Hao TSAI, Yi-Shiuan CHERNG, Wei-Yen CHIU
  • Publication number: 20250096146
    Abstract: A semiconductor device includes a substrate having a plurality of chip regions. In some embodiments, the semiconductor device further includes a plurality of scribe lines interposing the plurality of chip regions. In some examples, the semiconductor device further includes a first plurality of alignment mark regions distributed within the plurality of scribe lines. In some embodiments, the semiconductor device further includes a second plurality of alignment mark regions distributed within each of the plurality of chip regions.
    Type: Application
    Filed: January 24, 2024
    Publication date: March 20, 2025
    Inventors: Hao Chu Liao, Wei Tse Hsu, Chen-Yen Kao
  • Publication number: 20250095908
    Abstract: The network transformer includes an iron core body, and first, second, and third winding assemblies. The iron core body has first and second winding sections. A first flange and a second flange are on both ends of the iron core body, and a third flange situated between the first and second flanges. The first winding section is positioned between the first and third flange s, while the second winding section is located between the second and third flanges. The first, second, and third flanges respectively have first, second, and third electrode sets. The two ends of the coils in the first winding assembly are electrically connected to the first electrode set. The second winding assembly has the two ends of the coils electrically connected to the third electrode set. The third winding assembly has the two ends of the coils electrically connected to the second and third electrode sets.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 20, 2025
    Inventors: Ming-Yen Hsieh, Pao-Lin Shen, Hsiang-Chung Yang, Wei-Hsuan Lo
  • Publication number: 20250096203
    Abstract: A manufacturing method of a semiconductor package includes the following steps. A first lower semiconductor device and a second lower semiconductor device are provided. A plurality of first conductive pillars are formed on the first lower semiconductor device along a first direction parallel to a side of the first lower semiconductor device. A plurality of second conductive pillars are formed on the second lower semiconductor device along a second direction parallel to a side of the second lower semiconductor device, wherein the first direction is substantially collinear with the second direction. An upper semiconductor device is disposed on the first lower semiconductor device and the second lower semiconductor device and revealing a portion where the plurality of first conductive pillars and the plurality of second conductive pillars are disposed.
    Type: Application
    Filed: November 7, 2024
    Publication date: March 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo-Lung Pan, Ting Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
  • Patent number: 12255392
    Abstract: A wideband antenna system includes a first metal radiation portion, having a coupling distance with a second metal radiation portion; a first feeding contact and a second feeding contact, electrically connected to the first metal radiation portion and the second metal radiation portion respectively, and close to the coupling distance; a first ground contact, electrically connected to the second metal radiation portion; a second ground contact, electrically connected to the first metal radiation portion; an impedance tuner, electrically connected to the first feeding contact, the second feeding contact, the first ground contact, the second ground contact, and a radio frequency signal source, to switch the first metal radiation portion and the second metal radiation portion; an aperture contact, electrically connected to the first metal radiation portion; and an aperture tuner, electrically connected to the aperture contact.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: March 18, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chun-Chieh Su, Wei-Cheng Lo, Chien-Ming Hsu, Che-Yen Lin, Chuan-Chien Huang
  • Publication number: 20250087608
    Abstract: In an embodiment, a method includes forming a device layer over a first substrate; forming a first interconnect structure over a front-side of the device layer; attaching a second substrate to the first interconnect structure; forming a second interconnect structure over a back-side of the device layer, the second interconnect structure comprising back-side memory elements, wherein the back-side memory elements and a first plurality of active devices of the device layer provide a first memory array; and forming conductive connectors over the second interconnect structure.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 13, 2025
    Inventors: Chuei-Tang Wang, Wei Ling Chang, Chieh-Yen Chen, Chen-Hua Yu
  • Publication number: 20250087652
    Abstract: A semiconductor package includes an interposer that has a first side and a second side opposing the first side. A semiconductor device that is on the first side of the interposer and an optical device that is on the first side of the interposer and next to the semiconductor device. A first encapsulant layer includes a first portion and a second portion. The first portion of the first encapsulant layer is on the first side of the interposer and along sidewalls of the semiconductor device. A gap is between a first sidewall of the optical device and a second sidewall of the first portion of the first encapsulant layer. A substrate is over the second side of the interposer. The semiconductor device and the optical device are electrically coupled to the substrate through the interposer.
    Type: Application
    Filed: January 5, 2024
    Publication date: March 13, 2025
    Inventors: Wei-Yu Chen, Cheng-Shiuan Wong, Chia-Shen Cheng, Hsuan-Ting Kuo, Hao-Jan Pei, Hsiu-Jen Lin, Mao-Yen Chang
  • Publication number: 20250089360
    Abstract: A method includes forming a fin structure over a bottom dielectric isolator and a substrate. The fin structure includes a bottom channel layer, a sacrificial layer over the bottom channel layer, and a top channel layer over the sacrificial layer. A dummy gate is formed across the fin structure. Portions of the fin structure not covered by the gate structure are removed to expose a top surface of the bottom dielectric isolator. First source/drain epitaxial structures are epitaxially grown over the bottom dielectric isolator and are connected to the bottom channel layer. Second source/drain epitaxial structures are epitaxially grown over the first source/drain epitaxial structures and are connected to the top channel layer. The dummy gate and the sacrificial layer are replaced with a gate structure.
    Type: Application
    Filed: September 12, 2023
    Publication date: March 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-Ming LIEN, Wei-Yen WOON, Hung-Kun LO
  • Publication number: 20250076607
    Abstract: A camera structure, including a lens holder, a lens frame and a plurality of balls. The lens holder has a holder body, one end of which has a first rolling groove. The first groove wall part and the second groove wall part are disposed on two sides of the first rolling groove, and the groove bottom is disposed between the first groove wall part and the second groove wall part. The lens frame is mounted on an outer side of the holder body. The plurality of balls are located inside the first rolling groove, wherein the first groove wall part and the second groove wall part support the plurality of balls, there is a gap between each of the plurality of balls and the groove bottom, and the plurality of balls lay between the lens holder and the lens frame.
    Type: Application
    Filed: May 29, 2024
    Publication date: March 6, 2025
    Applicant: Lanto Electronic Limited
    Inventors: Ngoc-Luong NGUYEN, Wei-Han HSIA, Po-Ying TSENG, Wen-Yen HUANG, Shang-Yu HSU, Fu-Yuan WU
  • Publication number: 20250079316
    Abstract: A semiconductor device and an isolation structure and a contact etch stop layer thereof are provided. According to an embodiment of the present disclosure, a semiconductor device is provided, which includes a first dielectric layer and a second dielectric layer. The first dielectric layer is deposited on the sidewall of an active device or formed in a trench of a gate structure. The second dielectric layer covers the first dielectric layer, wherein the dielectric constant of the first dielectric layer is between 2 and 2.5, and the dielectric constant of the second dielectric layer is less than or equal to 4. In some embodiments, a dielectric bilayer is composed of amorphous boron nitride and crystalline boron nitride.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Hua CHEN, Jui-Chien HUANG, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20250080211
    Abstract: An antenna structure includes an upper patch antenna, a lower patch antenna, a grounding layer, a transmission line layer, and a first feeding line and a second feeding line passing through the grounding layer. Each of the first feeding line and the second feeding line includes a first portion, a second portion and a third portion. The first portion is disposed between the lower patch antenna and the grounding layer and is perpendicular to the grounding layer. The second portion is disposed between the grounding layer and the transmission line layer and is perpendicular to the grounding layer. The third portion is disposed within the grounding layer and is parallel to the grounding layer. The third portion is coupled between the first portion and the second portion.
    Type: Application
    Filed: June 20, 2024
    Publication date: March 6, 2025
    Inventors: Kun Yen TU, Meng-Hua TSAI, Sin-Siang WANG, Wei Ting LEE, Ming-Hsiang HUANG
  • Publication number: 20250081668
    Abstract: A chip package includes a semiconductor substrate, an anti-reflection layer, and a metal multi-layer. The semiconductor substrate has an optical sensing area. The anti-reflection layer is located on the semiconductor substrate. The metal multi-layer is located on and in contact with the anti-reflection layer. The metal multi-layer includes a redistribution line and two probe pads. Two ends of the redistribution line respectively extend to the two probe pads. The redistribution line is located in the optical sensing area, and the two probe pads are located outside the optical sensing area. The orthographic projection area of the redistribution line in the optical sensing area is less than 1% of the area of the optical sensing area.
    Type: Application
    Filed: August 13, 2024
    Publication date: March 6, 2025
    Inventors: Wei-Luen SUEN, Po-Jung CHEN, Jiun-Yen LAI, Tsang Yu LIU
  • Patent number: 12243915
    Abstract: The present disclosure provides source/drain epitaxial structures and source/drain contacts wrapped with graphene layers in fin structures of field effect transistors, and fabricating methods thereof. In some embodiments, a disclosed semiconductor device includes a fin structure on a substrate. The fin structure includes an epitaxial region. The semiconductor device further includes a metal contact above the epitaxial region, and a graphene film covering a top surface and sidewalls of the epitaxial region and covering a bottom surface and sidewalls of the metal contact.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Wei-Yen Woon
  • Publication number: 20250071050
    Abstract: Various systems, devices, storage media, and methods are discussed for selecting communication paths based upon health status in a hub and spoke communication network.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Applicant: Fortinet, Inc.
    Inventors: Kun Yu, Xiang Fan, Yanheng Wei, Di Liang, Chih Ho Yen
  • Publication number: 20250066899
    Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Inventors: Chun-Yen LIAO, I. LEE, Shu-Lan CHANG, Sheng-Hsuan LIN, Feng-Yu CHANG, Wei-Jung LIN, Chun-I TSAI, Chih-Chien CHI, Ming-Hsing TSAI, Pei Shan CHANG, Chih-Wei CHANG
  • Publication number: 20250071904
    Abstract: An integrated coil module includes: a substrate; a plurality of inductor elements arranged on the substrate with a spacing distance between adjacent inductor elements, the inductor elements each including an iron core, first and second coils wound on the iron core, first and second flanges at two sides of the iron core, and a third flange arranged on the iron core and between the first and second flanges, the first flange including first and second electrodes, the second flange including third and fourth electrodes, the third flange including fifth and sixth electrodes; and a plate arranged atop the plurality of inductor elements to cover the inductor elements. As such, the plurality of inductor elements are integrated together as a one-piece structure to thereby simplify the SMT manufacturing process and shorten the spacing distance between the inductor elements so as to reduce the area of the substrate occupied thereby.
    Type: Application
    Filed: August 21, 2023
    Publication date: February 27, 2025
    Inventors: Ming-Yen Hsieh, Pao-Lin Shen, Hsiang-Chung Yang, Wei-Hsuan Lo
  • Patent number: 12237398
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
  • Patent number: 12236903
    Abstract: A display device and a backlight control method of the display device are provided. When a duration of an image occlusion period is shorter than a preset duration, a backlight driving circuit is controlled to respectively provide a first pulse current and a second pulse current in a first light emitting period and a second light emitting period in each frame period, so as to drive a backlight unit to provide a first backlight and a second backlight. Here, the first pulse current is greater than the second pulse current.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: February 25, 2025
    Assignee: Qisda Corporation
    Inventors: Chun-Chang Wu, Yi-Zong Jhan, Jen-Hao Liao, Tse-Wei Fan, Wei-Yu Chen, Fu-Tsu Yen, Feng-Lin Chen
  • Publication number: 20250056911
    Abstract: A chip package includes a semiconductor substrate, a light-transmissive plate, a bonding layer, and a light-shielding layer. The bonding layer is located between the semiconductor substrate and the light-transmissive plate. The semiconductor substrate, the bonding layer, and the light-transmissive plate jointly define a sidewall including a first region and a second region. The first region extends from the semiconductor substrate to the light-transmissive plate, and is recessed relative to the second region. The light-shielding layer covers the sidewall and includes an extending portion, a wide portion, and a narrow portion. The extending portion is located on a surface of the semiconductor substrate facing away from the bonding layer. The wide portion is located on the first region of the sidewall. The narrow portion is located on the second region of the sidewall.
    Type: Application
    Filed: June 21, 2024
    Publication date: February 13, 2025
    Inventors: Wei-Luen SUEN, Chien Wei CHANG, Zi-Yu LIAO, Jiun-Yen LAI, Tsang Yu LIU