Abstract: Semiconductor structures and method of forming the same are provided. A method according to the present disclosure includes providing an intermediate structure that includes an opening, conformally depositing a metal liner over the opening, depositing a dummy fill material over the metal liner, recessing the dummy fill material such that a portion of the metal liner is exposed, removing the exposed portion of the metal liner, removing the recessed dummy fill material, and after the removing of the recessed dummy fill material, depositing a metal fill layer over the opening.

Abstract: A method includes forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A first dipole film and a second dipole film are formed on the first gate dielectric and the second gate dielectric, respectively. The Dipole dopants in the first dipole film and the second dipole film are driven into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are then removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form first transistor and a second transistor, respectively.

Abstract: A method (300) for adjusting a detection area of an image to be captured by an image capturing device (402) comprises: detecting person appearances in the detection area from input images previously captured by the image capturing device (402) over a period of time (302); generating a map corresponding to the detection area based on the person appearances, wherein the map comprises a measure of the person appearances detected in each of a plurality of portions of the detection area across the input images (304); determining if a ratio of unutilized portions to the plurality of portions exceeds a threshold ratio (306); and adjusting the detection area such that a focus area within the detection area comprising a part of utilized portions is positioned at a center of the adjusted detection area of the image to be captured in response to the determination (308).

Abstract: Methods and systems involving automotive computing architectures with phased wake sequences and power control are disclosed herein. A disclosed automotive computing system includes at least three subsystems: a first subsystem that is in an always-on power domain, a second subsystem that is powered on from a sleep state in response to an event detected by the first subsystem, and a third subsystem that is powered on, from an off state, after the first subsystem and the second subsystem are powered on. The subsystems of the architecture can be activated in different phases based on a given scenario in which the automotive computing architecture is operating. The same subsystem can occupy a different phase in different scenarios. The phased wake sequences may conserve power without sacrificing utility and may be optimized for different scenarios and triggering events.

Abstract: A time division duplexed (TDD) frequency modulation continuous wave (FMCW) radar system includes P transmitter circuit chains and M receiver circuit chains. The P transmitter circuit chains are used to transmit a plurality of FMCW signals. A pth transmitter circuit chain is coupled to a single pole Op throw (SPQPT) radio frequency (RF) switch, the SPOT RF switch is coupled to Op antennas, Qp and P are positive integers, and p is a positive integer not larger than P. The M receiver circuit chains are used to receive a plurality of reflected FMCW signals. An mth receiver circuit chain is coupled to a single pole Nm throw (SPNmT) radio frequency (RF) switch, the SPNmT RF switch is coupled to Nm antennas, Nm and M are positive integers, and m is a positive integer not larger than M.

Abstract: This disclosure relates to automotive computing architectures and more specifically to specialized discrete scale out computational elements that enhance the performance of an automotive computing architecture in terms of efficient networking and sensor data processing. A disclosed automotive computing architecture includes a set of zones, a zonal network, a sensor in a first zone, and an actuator in a second zone. A discrete computational element, in the first zone, receives sensor data from the sensor according to a legacy protocol, and is programmed to process the sensor data to produce a command therefrom and packages the command in the legacy protocol with an Ethernet packet. A second discrete computational element, in a second zone, is coupled to the actuator and is programmed to receive the Ethernet packet with the command, unpack the command into the legacy protocol, and provide the command in the legacy protocol to the actuator.

Abstract: A method of forming a semiconductor structure includes forming a conductive feature in a first dielectric layer, forming a second dielectric layer over the conductive feature, forming an opening in the second dielectric layer to expose a top surface of the conductive feature, forming an inhibitor film at the top surface of the conductive feature, depositing a thermal conductive layer having a first portion on sidewalls of the opening and a second portion on a top surface of second dielectric layer, removing the inhibitor film to expose the top surface of the conductive feature, depositing a conductive material in the opening and on the second portion of the thermal conductive layer, removing a portion of the conductive material to expose the second portion of the thermal conductive layer, and forming a third dielectric layer on the second portion of the thermal conductive layer and on the second dielectric layer.

Abstract: Methods are taught for creating training data for a learning algorithm, training the learning algorithm with the training data and using the trained learning algorithm to suggest domain names to users. A domain name registrar may store activities of a user on a registrar website. Preferably, domain name searches, selected suggested domain names and domain names registered to the user are stored as the training data in a training database. The training data may be stored so that earlier activities act as inputs to the learning algorithm while later activities are the expected outputs of the learning algorithm.

Abstract: A semiconductor structure includes: a first fin portion and a second fin portion; a first device and a second device which are respectively disposed on front surfaces of the first and second fin portions, each of the first and second devices including a source/drain portion; an isolation portion disposed to separate the first fin portion from the second fin portion and to separate the first device from the second device; and a hard mask portion disposed beneath a back surface of the isolation portion, and including a main region and two sidewall regions that are respectively located at two opposite sides of the main region so as to separate the main region from the first and second fin portions. The sidewall regions are made of a material different from that of the isolation portion. The main region is made of a material different from the material of the sidewall regions.

Abstract: A low thermal budget dielectric material deposition process is provided. The dielectric material may be deposited using spin-on coating, and treated with a microwave plasma treatment. In some implementations, the dielectric material is used adjacent a contact feature of a CFET device, such as a contact feature providing connection to a source/drain region of a bottom transistor of a CFET device.

Abstract: A thermoelectric cooler (TEC) is positioned to move heat away from a hot spot on a semiconductor chip and toward a dielectric substrate. This approach to thermal management is particularly effective when used in conjunction with a buried rail and back side power delivery. The TEC may be in a layer that contains solder connections be between two device layers an IC package. Alternatively, the TEC may be in a metal interconnect structure over the semiconductor substrate such as in a passivation stack at the top of the metal interconnect structure. TECs at either of these locations may be formed by wafer-level processing.

Abstract: A moving device, applied in a nucleic acid extraction system and cooperated with a plurality of microtube components, the moving device includes: a workbench; a moving component, disposed on the workbench; a control element, disposed on the moving component and electrically connected to the moving component; a first motor, disposed on the moving component and electrically connected to the control element; a first rotating rod, connected to the first motor; a second motor, disposed on the moving component and electrically connected to the control element; a second rotating rod, connected to the second motor; and a telescopic component, disposed on the moving component corresponding to the first rotating rod and the second rotating rod, electrically connected to the control element, and movable between a first position and a second position.

Abstract: A connection cable (1) includes an insulation seat (10), a circuit board (20) and a protection cover (30). The insulation seat (10) includes a main body (11) formed with a slot (110) and a conduction opening (111). The conduction opening (111) is connected to the slot (110) and located on the bottom side of the main body (11). The circuit board (20) includes a substrate (21) and a plurality of conductive portions (22) disposed on the substrate (21). The substrate (21) is inserted in the slot (110). The conductive portions (22) are exposed from the conduction opening (111). The protection cover (30) is combined on the main body (11) to shield the conduction opening (111). The protection cover (30) is pushed by the dock connector (2) to expose the conduction opening (111) and to be separated from the main body (11).

Abstract: An electronic device including a plurality of pixels and a driving element is provided. Each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The driving element drives each first sub-pixel of the plurality of pixels.

Abstract: A mechanical keyboard is provided, which includes a plurality of mechanical keys, a circuit board, a plurality of first magnetic elements, a lower casing and a plurality of second magnetic elements. The mechanical keyboard has a key region and an edge region surrounding the key region. The mechanical keys are located in the key region. The circuit board is disposed beneath the mechanical keys. The first magnetic elements are disposed beneath the circuit board and distributed in the key region. The lower casing is disposed beneath the mechanical keys, the circuit board and the first magnetic elements. The second magnetic elements are disposed over the lower casing, in which the second magnetic elements respectively correspond to the first magnetic elements and respectively repel the first magnetic elements.

Abstract: The present disclosure relates to an integrated circuit (IC) structure. The IC structure includes a semiconductor device having a frontside and a backside opposite the frontside. A first interconnect structure disposed on the frontside of the semiconductor device. The first interconnect structure comprises a first dielectric structure having a plurality of inter-level dielectric (ILD) layers. A second dielectric structure disposed on the backside of the semiconductor device. The second dielectric structure comprises a first high thermal conductivity layer having a thermal conductivity greater than that of the ILD layers.

Abstract: A wireless management system includes a controller and energy storage units. Each of the energy storage units includes an energy storage device and a node substrate. The wireless management system is configured to select a first node substrate from the node substrates based on a signal strength of each of first request signals to join a local network by the controller. The wireless management system is further configured to select a second node substrate from the node substrates based on the signal strength of each of second request signals to join the local network by the first node substrate. The wireless management system is further configured to assign a serial number corresponds to each of the energy storage units based on the local network by the controller.

Abstract: In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.

Abstract: A method includes forming a first complementary Field-Effect Transistor (CFET) and a second CFET. The first CFET includes a first lower transistor, and a first upper transistor overlapping the first lower transistor. The second CFET includes a second lower transistor, and a second upper transistor overlapping the second lower transistor. The method further includes performing a first etching process to form a first opening, wherein the first etching process includes etching a first gate stack between the first upper transistor and the second upper transistor, and etching a second gate stack between the first lower transistor and the second lower transistor. The first opening is filled with a dielectric material to form a dielectric region. The method further includes performing a second etching process to etch a middle portion of the dielectric region and to form a second opening, and filling the second opening with a conductive material to form a through-via.

Abstract: This disclosure provides systems, methods, and devices for image processing that support enhanced white balancing operations. In a first aspect, a method of image processing includes receiving first image data obtained at a first aperture; determining a first output image frame based on the first image data by applying a first white balancing to at least a portion of the first image data; receiving second image data obtained at a second aperture; and determining a second output image frame based on the second image data by applying a second white balancing based on the first aperture and the second aperture to at least a portion of the second image data. The second white balancing may be based on a first compensation factor based on the first aperture and the second aperture used to adjust the first white balancing. Other aspects and features are also claimed and described.