Patents by Inventor Wei-Yi Hu
Wei-Yi Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145650Abstract: A package comprises a substrate including a first surface, and an upper conductive layer arranged on the first surface, a first light-emitting unit arranged on the upper conductive layer, and comprises a first semiconductor layer, a first substrate, a first light-emitting surface and a first side wall, a second light-emitting unit, which is arranged on the upper conductive layer, and comprises a second light-emitting surface and a second side wall, a light-transmitting layer arranged on the first surface and covers the upper conductive layer, the first light-emitting unit, and the second light-emitting unit, a light-absorbing layer, which is arranged between the substrate and the light-transmitting layer in a continuous configuration of separating the first light-emitting unit and the second light-emitting unit from each other, and a reflective wall arranged on the first side wall, wherein a height of the reflective wall is lower than that of the light-absorbing layer.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Inventors: Shau-Yi CHEN, Tzu-Yuan LIN, Wei-Chiang HU, Pei-Hsuan LAN, Min-Hsun HSIEH
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Patent number: 11941338Abstract: Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.Type: GrantFiled: July 26, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yi Hu, Chih-Ming Chao, Chi-Yeh Yu
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Publication number: 20240095439Abstract: Disclosed are semiconductor devices having an interconnection pattern that includes a plurality of parallel conductors including a first conductor aligned with a first axis and a first dummy pattern aligned with a second axis on a first side of the first axis and offset from the first axis by an axis offset distance LAO in which the first dummy pattern includes N dummy conductors having a first dummy conductor length LDC with the dummy conductors being separated by a dummy conductor-to-dummy conductor spacing EED.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Inventors: Wei-Yi HU, Chih-Ming CHAO, Jung-Chou TSAI
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Publication number: 20230289508Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.Type: ApplicationFiled: June 29, 2022Publication date: September 14, 2023Inventors: Chi-Yeh Yu, Wei-Yi Hu, Shih-Hsuan Chien, You-Cheng Xiao, Ya-Chi Chou
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Publication number: 20230142853Abstract: Disclosed are semiconductor devices having an interconnection pattern that includes a plurality of parallel conductors including a first conductor aligned with a first axis and a first dummy pattern aligned with a second axis on a first side of the first axis and offset from the first axis by an axis offset distance LAO in which the first dummy pattern includes N dummy conductors having a first dummy conductor length LDC with the dummy conductors being separated by a dummy conductor-to-dummy conductor spacing EED.Type: ApplicationFiled: January 11, 2023Publication date: May 11, 2023Inventors: Wei-Yi HU, Chih-Ming CHAO, Jung-Chou TSAI
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Patent number: 11556691Abstract: Disclosed are methods for designing semiconductor devices, conductive layer patterns, and interconnection layer patterns including the operations of analyzing an initial semiconductor design layout to identify excessive open spaces between adjacent conductive elements or lines within an interconnection layer pattern, selecting or generating a dummy pattern to fill a portion of the open space, and generating a modified semiconductor design layout that incorporates the dummy pattern into first interconnection layer pattern to reduce the open space.Type: GrantFiled: September 17, 2019Date of Patent: January 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Yi Hu, Chih-Ming Chao, Jung-Chou Tsai
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Publication number: 20220358276Abstract: Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yi HU, Chih-Ming CHAO, Chi-Yeh YU
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Patent number: 11487924Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: GrantFiled: June 11, 2021Date of Patent: November 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Sheng Chen, Ching-Yu Chai, Wei-Yi Hu
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Patent number: 11443094Abstract: Methods for inserting dummy boundary cells in an integrated circuit (IC) are provided. A plurality of macros and a top channel are merged into floorplan of the IC. The top channel is arranged between the macros and is filled with a plurality of first dummy boundary cells, and each of the macros includes a macro boundary and a main pattern surrounded by the macro boundary. The first dummy boundary cells within the top channel and between a first macro and a second macro are replaced with a plurality of second dummy boundary cells. The macro boundaries of the first and second macros are formed by the second dummy boundary cells. First gate length of dummy patterns within the first dummy boundary cells is greater than second gate length of dummy patterns within the second dummy boundary cells. The first and second dummy boundary cells are the same size.Type: GrantFiled: May 28, 2020Date of Patent: September 13, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Yi Hu, Chih-Ming Chao, Chi-Yeh Yu
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Publication number: 20210303765Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: ApplicationFiled: June 11, 2021Publication date: September 30, 2021Inventors: CHIN-SHENG CHEN, CHING-YU CHAI, WEI-YI HU
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Patent number: 11048841Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: GrantFiled: May 15, 2020Date of Patent: June 29, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Sheng Chen, Ching-Yu Chai, Wei-Yi Hu
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Publication number: 20210042461Abstract: Methods for inserting dummy boundary cells in an integrated circuit (IC) are provided. A plurality of macros and a top channel are merged into floorplan of the IC. The top channel is arranged between the macros and is filled with a plurality of first dummy boundary cells, and each of the macros includes a macro boundary and a main pattern surrounded by the macro boundary. The first dummy boundary cells within the top channel and between a first macro and a second macro are replaced with a plurality of second dummy boundary cells. The macro boundaries of the first and second macros are formed by the second dummy boundary cells. First gate length of dummy patterns within the first dummy boundary cells is greater than second gate length of dummy patterns within the second dummy boundary cells. The first and second dummy boundary cells are the same size.Type: ApplicationFiled: May 28, 2020Publication date: February 11, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Yi HU, Chih-Ming CHAO, Chi-Yeh YU
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Publication number: 20200279063Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: ApplicationFiled: May 15, 2020Publication date: September 3, 2020Inventors: CHIN-SHENG CHEN, CHING-YU CHAI, WEI-YI HU
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Patent number: 10678982Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: GrantFiled: October 29, 2018Date of Patent: June 9, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Sheng Chen, Ching-Yu Chai, Wei-Yi Hu
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Publication number: 20200104461Abstract: Disclosed are methods for designing semiconductor devices, conductive layer patterns, and interconnection layer patterns including the operations of analyzing an initial semiconductor design layout to identify excessive open spaces between adjacent conductive elements or lines within an interconnection layer pattern, selecting or generating a dummy pattern to fill a portion of the open space, and generating a modified semiconductor design layout that incorporates the dummy pattern into first interconnection layer pattern to reduce the open space.Type: ApplicationFiled: September 17, 2019Publication date: April 2, 2020Inventors: Wei-Yi HU, Chih-Ming CHAO, Jung-Chou TSAI
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Patent number: 10509883Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.Type: GrantFiled: January 24, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsun-Yu Yang, Wei-Yi Hu, Jui-Feng Kuan, Hsien-Hsin Sean Lee, Po-Cheng Pan, Hung-Wen Huang, Hung-Ming Chen, Abhishek Patyal
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Publication number: 20190065647Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: ApplicationFiled: October 29, 2018Publication date: February 28, 2019Inventors: CHIN-SHENG CHEN, CHING-YU CHAI, WEI-YI HU
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Patent number: 10169507Abstract: An integration circuit (IC) simulation method includes: (a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; (b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters; (c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavioral model; and (d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation.Type: GrantFiled: February 22, 2017Date of Patent: January 1, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Cheng Kuo, Wei-Yi Hu
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Patent number: 10127338Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: GrantFiled: December 15, 2015Date of Patent: November 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Sheng Chen, Ching-Yu Chai, Wei-Yi Hu
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Patent number: 10019540Abstract: A method is disclosed that includes performing a first simulation by applying first variations to identify at least one sample of an integrated circuit (IC), wherein the IC comprises at least one device; translating individual variables of split devices implementing the at least one device, to an equivalent variable for the split devices; and performing a second simulation, by applying at least a portion of second variations, with the equivalent variable for the split devices, to obtain a simulation result serving as a basis of modifying the layout for fabrication of the IC.Type: GrantFiled: December 30, 2015Date of Patent: July 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Cheng Kuo, Wei-Yi Hu, Kuang-Ming Wang