Abstract: A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification.

Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.

Abstract: An integration circuit (IC) simulation method includes: (a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; (b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters; (c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavioral model; and (d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation.

Abstract: A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.

Abstract: A method is disclosed that includes performing a first simulation by applying first variations to identify at least one sample of an integrated circuit (IC), wherein the IC comprises at least one device; translating individual variables of split devices implementing the at least one device, to an equivalent variable for the split devices; and performing a second simulation, by applying at least a portion of second variations, with the equivalent variable for the split devices, to obtain a simulation result serving as a basis of modifying the layout for fabrication of the IC.

Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.

Abstract: In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.

Abstract: A system for designing an integrated circuit includes at least one processor and at least one memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to receive a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from a set of system design rule constraints. The system is also caused to revise a schematic of the integrated circuit including the proposed device array layout. The system is further caused to determine whether the revised schematic violates one or more system design rule constraints.

Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

Abstract: A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification.

Abstract: A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.

Abstract: A system for designing an integrated circuit includes at least one processor and at least one memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to receive a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from a set of system design rule constraints. The system is also caused to revise a schematic of the integrated circuit including the proposed device array layout. The system is further caused to determine whether the revised schematic violates one or more system design rule constraints.

Abstract: A method of designing a fin field effect transistor (FinFET)-based circuit includes designing, using a processor, a first circuit schematic design based on a performance specification, the first circuit schematic design is free of artificial elements, wherein the artificial elements are used to simulate electrical performance of the FinFET-based circuit. The method further includes modifying, using the processor, at least one device within the first circuit schematic design to form a second circuit schematic design taking the artificial elements into consideration. The method further includes performing a pre-layout simulation using the second circuit schematic and taking the artificial elements into consideration. The method further includes generating a layout, wherein the layout does not take the artificial elements into consideration, and performing a post-layout simulation, wherein the post-layout simulation does not take the artificial elements into consideration.

Abstract: A system for designing an integrated circuit generates a schematic of the integrated circuit based on a set of system design rule constraints. The system also receives a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from the set of system design rule constraints. The system further generates a revised schematic of the integrated circuit including the proposed device array layout. The system additionally determines if the revised schematic violates one or more of the system design rule constraints.

Abstract: A system for designing an integrated circuit generates a schematic of the integrated circuit based on a set of system design rule constraints. The system also receives a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from the set of system design rule constraints. The system further generates a revised schematic of the integrated circuit including the proposed device array layout. The system additionally determines if the revised schematic violates one or more of the system design rule constraints.

Abstract: A method of designing a fin field effect transistor (FinFET)-based circuit includes designing, using a processor, a first circuit schematic design based on a performance specification, the first circuit schematic design is free of artificial elements, wherein the artificial elements are used to simulate electrical performance of the FinFET-based circuit. The method further includes modifying, using the processor, at least one device within the first circuit schematic design to form a second circuit schematic design taking the artificial elements into consideration. The method further includes performing a pre-layout simulation using the second circuit schematic and taking the artificial elements into consideration.

Abstract: In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.

Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

Abstract: In some embodiments, in a method for considering in-phase grouping for a voltage-dependent design rule, for a first net and a second net in a schematic, first data for obtaining the differences between first voltage values of the first and second nets, and between second voltage values of the first and second nets is provided. For each of the first and second nets, the first voltage value is larger than the second voltage value. A layout for the schematic is generated. In the layout, a relationship of a first shape and a second shape associated with the first and the second nets, respectively, is defined using the first data.

Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.