Abstract: The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed.

Abstract: The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed.

Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

Abstract: An integrated circuit (IC) simulation method comprises providing a device process model from a non-transitory machine readable storage medium into a programmed computer. The device process model includes one or more device variables. Each device variable defines a probability distribution of an active-device-level variation of devices in an IC. A conductive line model and/or a multi patterning technology (MPT) model is provided from the storage medium to the computer. The conductive line model includes one or more conductive line variables. Each conductive line variable defines a probability distribution of a conductive-line process-induced variation. The MPT model includes one or more MPT variables. Each MPT variable defines a probability distribution of a mask-misalignment-induced conductive line coupling variation. A Monte Carlo simulation is performed in the computer, including the device process model and the conductive line model or MPT model, to identify parasitic couplings in the IC.

Abstract: Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.

Abstract: Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.

Abstract: A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.

Abstract: A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.

Abstract: A method of auto-I/Q calibration in modulator and demodulator, including DC cancellation, gain imbalance and phase error calibration is provided for implementation in a front-end circuit without the use of baseband processing signal. In modulator auto-I/Q calibration, the gain amplifier, peak detector, DC gain cell and comparator and auto-I/Q calibration control logic form a calibration loop between modulator output and input buffer. The DC test vectors for their corresponding calibrations are applied to modulator to determine I/Q mismatch. In the calibration loop, the peak detector convert the carrier leakage, differential signal power level caused by the I/Q path gain mismatch and by the local quadrature mismatch into DC signal power level. The comparator is used to measure the DC different on peak deter output under different input test vector.