Abstract: Method of forming a switch bracket of a hinge for a two-body information handling system, including mixing metal powders and binders to form a blended mix; pelletizing the blended mix to form feedstock; injecting the feedstock into a switch bracket mold cavity to form a first article of the switch bracket; de-binding the first article to remove the binders from the first article forming a second article of the switch bracket; and sintering the second article by shrinking the second article to form the switch bracket.

Abstract: The invention provides a three-dimensional (3D) image display method and a display device with a 3D image display function. The 3D image display method includes the following. A display device coordinate system is established. First volume data is obtained, and multiple first coordinates of multiple voxels of the first volume data in an absolute space coordinate system are defined. The multiple first coordinates of the multiple voxels of the first volume data are converted to the display device coordinate system to generate second volume data. Display data is generated according to the second volume data. An image is displayed according to the display data through the display device, and the image forms a 3D image with a 3D object image in human eyes, in which the 3D object image changes equally or proportionally in response to a change desired by a user through an input unit.

Abstract: A flexible display input device includes a flexible display layer and a keyswitch layer. The keyswitch layer is disposed under the flexible display layer and includes a first elastic film, a first electrode, a second elastic film, and a second electrode. The first electrode is disposed on a side of the first elastic film facing toward the flexible display layer. The second elastic film is located between the flexible display layer and the first elastic film. The second electrode is disposed on a side of the second elastic film facing toward the first elastic film and is opposite to the first electrode.

Abstract: A method of performing pulsed remote plasma etching includes arranging a substrate in a processing chamber configured to perform pulsed remote plasma etching, setting at least one process parameter of the processing chamber, supplying at least one gas mixture to an upper chamber region of the processing chamber, supplying, in an ON period, a first voltage to coils arranged around the upper chamber region to energize the at least one gas mixture and generate plasma within the upper chamber region of the processing chamber, turning off the first voltage in an OFF period to discontinue generating plasma within the upper chamber region of the processing chamber, and alternating between supplying the first voltage in the ON period and turning off the first voltage in the OFF period to generate pulsed remote plasma within the upper chamber region of the processing chamber.

Abstract: Methods and systems for processing a bevel edge of a wafer in a bevel plasma chamber. The method includes receiving a pulsed mode setting for a RF generator of the bevel plasma chamber. The method includes identifying a duty cycle for the pulsed mode, the duty cycle defining an ON time and an OFF time during each cycle of power delivered by the generator. The method includes calculating or accessing a compensation factor to an input RF power setting of the generator. The compensation factor is configured to add an incremental amount of power to the input power setting to account for a loss in power attributed to the duty cycle to be run in the pulsed mode. The method is configured to run the generator in the pulse mode with the duty cycle and the pulsing frequency.

Abstract: A circuit for performing energy-efficient and high-throughput multiply-accumulate (MAC) arithmetic dot-product operations and convolution computations includes a two dimensional crossbar array comprising a plurality of row inputs and at least one column having a plurality of column circuits, wherein each column circuit is coupled to a respective row input. Each respective column circuit includes an excitatory memristor neuron circuit having an input coupled to a respective row input, a first synapse circuit coupled to an output of the excitatory memristor neuron circuit, the first synapse circuit having a first output, an inhibitory memristor neuron circuit having an input coupled to the respective row input, and a second synapse circuit coupled to an output of the inhibitory memristor neuron circuit, the second synapse circuit having a second output. An output memristor neuron circuit is coupled to the first output and second output of each column circuit and has an output.

Abstract: The present disclosure provides a system and method for adjusting display brightness. The method includes determining a color of a bezel surrounding a display and automatically adjusting a brightness of the display based on the color of the bezel.

Abstract: An electronic device with an auxiliary lighting function and an operation method thereof are provided. The electronic device includes a first body, a display screen, and a light-emitting module. The first body has a first surface. The first surface includes a screen area and a border area. The border area surrounds the screen area. The display screen is disposed in the screen area of the first body. The light-emitting module is disposed in the border area of the first body. The light-emitting module provides an illumination light in at least one first area of the border area, and provides an indicating light in at least one second area of the border area.

Abstract: A bit index explicit replication (BIER) operations, administration, and maintenance (OAM) detection method includes a bit forwarding ingress router (BFIR) obtaining a detection request packet based on a first BIER OAM packet, and sending the detection request packet to at least one bit forwarding egress router BFER. The detection request packet includes a first packet and a first packet header. The first packet is a packet obtained by encapsulating the first BIER OAM packet. The first packet header includes a bit string, and the bit string indicates the at least one bit forwarding egress router BFER that is to be measured.

Abstract: Disclosed are semiconductor devices having an interconnection pattern that includes a plurality of parallel conductors including a first conductor aligned with a first axis and a first dummy pattern aligned with a second axis on a first side of the first axis and offset from the first axis by an axis offset distance LAO in which the first dummy pattern includes N dummy conductors having a first dummy conductor length LDC with the dummy conductors being separated by a dummy conductor-to-dummy conductor spacing EED.

Abstract: Systems and methods of conducting a bar code scan using an imaging-based bar code scan device are provided. In one exemplary embodiment, a method is performed by an imaging-based bar code device that includes processing circuitry, an optical lens assembly having an image sensor and an optical lens with a focused region at a certain distance in front of the optical lens along an optical axis of the optical lens, a plurality of light emitting elements configured proximate the optical lens and laterally offset from the optical axis. The method includes sending, by the processing circuitry, to each light emitting element, an indication to enable that light emitting element to project a light beam towards the optical axis in the focused region so that the light beams overlap when a target bar code is in the focused region and non-overlap when a target bar code is outside the focused region.

Abstract: The present application relates to the field of communications technologies, and provides a method for controlling a radio frequency front-end device and user equipment, where the user equipment includes a processor and the radio frequency front-end device, and the method includes: receiving, by the radio frequency front-end device, a switch control instruction from the processor, where the switch control instruction is an instruction sent by the processor to the radio frequency front-end device at a first moment; and performing, by the radio frequency front-end device, on-off switching in response to the switch control instruction.

Abstract: A memory circuit configured to perform multiply-accumulate (MAC) operations for performance of an artificial neural network includes a series of synapse cells arranged in a cross-bar array. Each cell includes a memory transistor connected in series with a memristor. The memory circuit also includes input lines connected to the source terminal of the memory transistor in each cell, output lines connected to an output terminal of the memristor in each cell, and programming lines coupled to a gate terminal of the memory transistor in each cell. The memristor of each cell is configured to store a conductance value representative of a synaptic weight of a synapse connected to a neuron in the artificial neural network, and the memory transistor of each cell is configured to store a threshold voltage representative of a synaptic importance value of the synapse connected to the neuron in the artificial neural network.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce temperature of a networked device. An example apparatus includes, a temperature threshold monitor to identify a temperature condition associated with the device, a window information retriever to retrieve a current value of a network receive capacity parameter, and a window adjustor to reduce the temperature of the device by generating a modified network receive capacity parameter, the modified network receive capacity parameter based on a ratio of the current value of the network receive capacity parameter and a decrease factor.

Abstract: An AC two-wire LED high voltage lamp string with synchronous dimming and color adjustment comprises a high voltage controller and a lamp string group, wherein the high voltage controller comprises a control box, and a first power supply module, a switch control circuit and a first microcontrol unit which are arranged in the control box and connected in sequence; the first power supply module is connected with the switch control circuit and the first microcontrol unit; a second microcontrol unit. The present invention modulates and encodes a high voltage sine wave using the switch control circuit at the controller end and demodulates the sine wave at a bulb end to realize the functions of color change timing, flashing, timing and light control of lamp strings. The lamp strings can be used individually or connected in series and in parallel for use, to satisfy different needs of consumers.

Abstract: Disclosed are methods for designing semiconductor devices, conductive layer patterns, and interconnection layer patterns including the operations of analyzing an initial semiconductor design layout to identify excessive open spaces between adjacent conductive elements or lines within an interconnection layer pattern, selecting or generating a dummy pattern to fill a portion of the open space, and generating a modified semiconductor design layout that incorporates the dummy pattern into first interconnection layer pattern to reduce the open space.

Abstract: A three-dimensional sensing module includes a touch pressure sensing structure. The touch pressure sensing structure includes a first functional spacer layer, a first light-transmitting electrode layer coated on the first functional spacer layer, a second functional spacer layer coated on the first light-transmitting electrode layer, a second light-transmitting electrode layer coated on the second functional spacer layer, and a third functional spacer layer coated on the second light-transmitting electrode layer. Resistivities of the first, second, and third functional spacer layers are greater than resistivities of the first and second light-transmitting electrode layers.

Abstract: A memory circuit configured to perform multiply-accumulate (MAC) operations for performance of an artificial neural network includes a series of synapse cells arranged in a cross-bar array. Each cell includes a memory transistor connected in series with a memristor. The memory circuit also includes input lines connected to the source terminal of the memory transistor in each cell, output lines connected to an output terminal of the memristor in each cell, and programming lines coupled to a gate terminal of the memory transistor in each cell. The memristor of each cell is configured to store a conductance value representative of a synaptic weight of a synapse connected to a neuron in the artificial neural network, and the memory transistor of each cell is configured to store a threshold voltage representative of a synaptic importance value of the synapse connected to the neuron in the artificial neural network.