Patents by Inventor Wei-Yu Lin

Wei-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220246715
    Abstract: A capacitor unit and a manufacturing process thereof are provided. The manufacturing process includes: providing a carrier; forming a metallic layer on the carrier, defining a plurality of metallic blocks in the metallic layer, and forming a middle stacking structure on each of the metallic blocks, wherein the middle stacking structure includes a first capacitance conductive layer, a second capacitance conductive layer, and a capacitance insulation layer located between the first and second capacitance conductive layers, wherein the first capacitance conductive layer is electrically connected to the corresponding one of the metallic blocks; and removing the carrier to expose the metallic blocks so as to form a plurality of independent capacitor units, so as to fabricate double sided capacitor units with high capacitance.
    Type: Application
    Filed: August 1, 2021
    Publication date: August 4, 2022
    Inventors: KUO-YU YEH, WEI-YU LIN
  • Patent number: 11404113
    Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsin Nien, Wei-Chang Zhao, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen, Ru-Yu Wang
  • Publication number: 20220234463
    Abstract: A charging apparatus for use with an electric vehicle includes a power transmission path, a switch, a first controller, a communication unit, and a second controller. The switch is disposed on the power transmission path. The communication unit is coupled to a second connection port. The first controller is coupled to the power transmission path, the switch, the second controller, and the communication unit. When the second controller receives a first request from a power management system and correspondingly notifies the first controller, the first controller switches from a first signal to a second signal to communicate with the electric vehicle and turns off the switch, and when the first controller receives a first EV notification provided from the electric vehicle, the controller turns on the switch.
    Type: Application
    Filed: September 1, 2021
    Publication date: July 28, 2022
    Inventors: Jui-Yuan HSU, Wei-Hsun LAI, Ming-Yu JIANG, Bo-Song LIN, Jung-Lien SHIH
  • Publication number: 20220238800
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
    Type: Application
    Filed: February 22, 2021
    Publication date: July 28, 2022
    Inventors: Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai, Da-Jun Lin, Chau-Chung Hou, Wei-Xin Gao
  • Publication number: 20220230889
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Inventors: Yen-Hao CHEN, Wei-Han LAI, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20220231116
    Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Inventors: Wei-Yu CHOU, Yang-Che CHEN, Chen-Hua LIN, Victor Chiang LIANG, Huang-Wen TSENG, Chwen-Ming LIU
  • Publication number: 20220230806
    Abstract: A capacitor integrated structure, a capacitor unit and a manufacturing process thereof are provided. The manufacturing process of capacitor units includes the steps of: forming a plurality of capacitor stacking structures on a substrate having an insulation layer thereon; performing a first cut on insulation dividers provided between the adjacent capacitor stacking structures to form a plurality of recesses that expose first conductive portion and second conductive portion of each of the capacitor stacking structures; filling a metallic material in the recesses to form a plurality of metallic dividers that are electrically connected to the first conductive portion and the second conductive portion of each of the capacitor stacking structures; performing a second cut on the metallic dividers to form a plurality of independent capacitor units; and forming metallic walls on two opposite sides of each of the capacitor units, so as to provide a capacitor unit having two end electrodes.
    Type: Application
    Filed: June 19, 2021
    Publication date: July 21, 2022
    Inventors: WEI-YU LIN, KUO-YU YEH
  • Patent number: 11393769
    Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Publication number: 20220224378
    Abstract: A method for downlink transmission in a cloud radio access network for a number of users is applied in a central unit. The central unit determines a specific number of remote radio heads (RRHs) as non-serving RRHs based on a predetermined data compression ratio. For each of many pieces of user equipment (UEs), the central unit determines a combination of RRHs which are non-serving in coordinated multi-point transmission (CoMP) from a plurality of RRHs based on the determined specific number, and then performs CoMP downlink transmission based on the combination of RRHs which are non-serving in the CoMP.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Inventors: TZU-YU LIN, SHANG-HO TSAI, YU-HENG YOU, HSIN-HUNG CHOU, WEI-HAN HSIAO
  • Publication number: 20220216071
    Abstract: A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Inventors: Wei-Yu Chen, Hao-Jan Pei, Hsuan-Ting Kuo, Chih-Chiang Tsao, Jen-Jui Yu, Philip Yu-Shuan Chung, Chia-Lun Chang, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20220196549
    Abstract: The disclosure provides a calibration assembly for a scan device. The calibration assembly includes a plurality of light-permeable plates and a reflection plate. The light-permeable plates are different in size, and the light-permeable plates are arranged along thicknesses directions thereof to form a step shape. The light-permeable plates define a plurality of light-permeable areas that respectively have different numbers of layers of the light-permeable plates inversely proportional to transmittances of the light-permeable areas. The light-permeable areas are configured to be permeable to a light having a predetermined frequency. The reflection plate is disposed at a side of one of the light-permeable plates in the thickness direction thereof. The reflection plate has a plurality of first holes having different sizes, and the reflection plate is configured to block the light having the predetermined frequency. The disclosure also provides a calibration system having the calibration assembly.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Tai LI, Wei-Yu LIN, Chia-Jen LIN, Chin LIEN, Cho-Fan HSIEH
  • Patent number: 11289470
    Abstract: A method of manufacturing a trench transistor structure including the following steps is provided. A substrate structure is provided. A first region and a second region are defined in the substrate structure. The substrate structure has a first trench located in the first region and a second trench located in the second region. A transistor device is formed in the first region. The transistor device includes an electrode located in the first trench. The electrode and the substrate structure are isolated from each other. An electrostatic discharge (ESD) protection device is formed in the second region. The ESD protection device includes a main body layer located in the second trench. The main body layer has a planarized top surface. PN junctions are located in the main body layer. The main body layer and the substrate structure are isolated from each other.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: March 29, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wei-Yu Lin, Shih-Hao Cheng
  • Publication number: 20220068568
    Abstract: A capacitor unit formed by a capacitor integrated structure is provided. The capacitor integrated structure is cut to form capacitor units separated from each other, and each of the capacitor units includes: a substrate; an isolation layer located on the substrate; a capacitor stacked structure located on the isolation layer, wherein the isolation layer electrically isolates the substrate from the capacitor stacked structure; and two electrode connectors located on the capacitor stacked structure and being exposed.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wei-Yu Lin, Shih-Hao Cheng
  • Patent number: 11211203
    Abstract: A capacitor unit and a manufacturing method thereof are provided. The manufacturing method includes the following steps. An isolation layer is formed on a substrate. A first capacitor stacked structure and a second capacitor stacked structure are formed on the isolation layer. Electrode connectors are formed on the first capacitor stacked structure and the second capacitor stacked structure. The electrode connectors are exposed, so that the electrode connectors, the first capacitor stacked structure, the second capacitor stacked structure, the isolation layer, and the substrate are combined to form a capacitor integrated structure, wherein the isolation layer electrically isolates the substrate from the first capacitor stacked structure and the second capacitor stacked structure. The capacitor integrated structure is cut to form a first capacitor unit and a second capacitor unit separated from each other.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: December 28, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wei-Yu Lin, Shih-Hao Cheng
  • Publication number: 20210397339
    Abstract: An example non-transitory computer-readable storage medium comprises instructions that, when executed by a processing resource of a computing device, cause the processing resource to present an interface of an application on a first display of the computing device. The instructions further cause the processing resource to, in response to receiving a selection of a boundary that defines a portion of the interface, present the portion on a second display of the computing device.
    Type: Application
    Filed: March 13, 2019
    Publication date: December 23, 2021
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Ron Yiran Zhang, Lu-Yen Lai, Wei-Yu Lin, Dhruv Jain, Cheng-Tsung Wu, Yannick Quentin Pivot
  • Publication number: 20210397399
    Abstract: An example non-transitory computer-readable storage medium comprises instructions that, when executed by a processing resource of a computing device, cause the processing resource to determine a portion of an interface moved from a first display to a second display. The instructions further cause the processing resource to compare the portion of the interface moved from the first display to the second display to a threshold. The instructions further cause the processing resource to move the interface automatically from the first display to the second display responsive to a determination that the portion of the interface moved to the second display exceeds the threshold.
    Type: Application
    Filed: March 12, 2019
    Publication date: December 23, 2021
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Ron Yirang Zhang, Lu-Yen Lai, Wei-Yu Lin, Dhruv Jain, Cheng-Tsung Wu
  • Publication number: 20210301032
    Abstract: The invention provides anti-KLK5 antibodies and methods of using the same.
    Type: Application
    Filed: November 17, 2020
    Publication date: September 30, 2021
    Applicant: Genentech, Inc.
    Inventors: Cecilia P.C. Chiu, Hilda Y. Hernandez-Barry, David B. Iaea, Moulay Hicham Alaoui-Ismaili, James T. Koerber, Wei Yu Lin, Kelly Loyet, Yonglian Sun, Benjamin T. Walters, Jawahar Sudhamsu
  • Publication number: 20210091067
    Abstract: A method of manufacturing a trench transistor structure including the following steps is provided. A substrate structure is provided. A first region and a second region are defined in the substrate structure. The substrate structure has a first trench located in the first region and a second trench located in the second region. A transistor device is formed in the first region. The transistor device includes an electrode located in the first trench. The electrode and the substrate structure are isolated from each other. An electrostatic discharge (ESD) protection device is formed in the second region. The ESD protection device includes a main body layer located in the second trench. The main body layer has a planarized top surface. PN junctions are located in the main body layer. The main body layer and the substrate structure are isolated from each other.
    Type: Application
    Filed: December 9, 2020
    Publication date: March 25, 2021
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wei-Yu Lin, Shih-Hao Cheng
  • Publication number: 20210036098
    Abstract: A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost.
    Type: Application
    Filed: January 13, 2020
    Publication date: February 4, 2021
    Inventors: WEI-YU LIN, CHUAN-CHIEH LIN, SHIH-HAO CHENG
  • Patent number: 10903203
    Abstract: A trench transistor structure includes a substrate structure, a transistor device, and an electrostatic discharge (ESD) protection device. A first region and a second region are defined in the substrate structure. The substrate structure has a first trench located in the first region and a second trench located in the second region. The transistor device is located in the first region and includes an electrode located in the first trench. The electrode and the substrate structure are isolated from each other. The ESD protection device is located in the second region and includes a main body layer located in the second trench. The main body layer has a planarized top surface. PN junctions are located in the main body layer. The main body layer and the substrate structure are isolated from each other.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: January 26, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wei-Yu Lin, Shih-Hao Cheng