Abstract: The present invention discloses a vessel power safety control system and operating method thereof. The vessel power safety control system includes a load power management module, a real-time monitoring module, an integration module and a power module. The present invention can assist the autonomous ship as any occurrence of fault during navigation. Once the accident occurs, the load power management module will give an instruction to control the DC bus to switch from closed circuit to open circuit to protect other equipment. After determining whether the errors of the equipment on board is eliminated, the load power management system performs automatic system reset procedure. As such, the DC bus can be converted from an open circuit to a closed circuit to restart the power supply for the facility.

Abstract: Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include forming a stack over a substrate, forming a fin-shape structure from patterning the stack and the substrate, recessing the fin-shape structure to form a source/drain trench, depositing a dielectric film in the source/drain trench with a top surface below a top surface of the substrate in the fin-shape structure, and forming an epitaxial feature over the dielectric film. A bottom surface of the epitaxial feature is below the top surface of the substrate in the fin-shape structure.

Abstract: The invention provides anti-KLK5 antibodies and methods of using the same.

Abstract: The invention provides anti-kallikrein-related peptidase 5 (KLK5) antibodies and methods of using the same.

Abstract: A capacitor structure including a substrate, a capacitor, a second dielectric layer, a first conductive layer, and a second conductive layer is provided. The capacitor includes first electrode layers, at least one second electrode layer, and a first dielectric layer. The first electrode layers and the at least one second electrode layer are alternately disposed on the substrate. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The second dielectric layer has first openings and at least one second opening. The first openings expose the first electrode layers. The second opening exposes the second electrode layer. The first conductive layer is electrically connected to the first electrode layers. The first conductive layer is a single conductive layer disposed on the second dielectric layer and extending into the first openings. The second conductive layer is electrically connected to the second electrode layer.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a first performance metric score may be determined based upon first content item text. A plurality of similarity scores associated with a plurality of sets of content item text may be determined. One or more sets of content item text may be selected from among the plurality of sets of content item text based upon the plurality of similarity scores and a plurality of performance metric scores associated with the plurality of sets of content item text. The plurality of performance metric scores may comprise one or more performance metric scores associated with the one or more sets of content item text. The one or more performance metric scores may be higher than the first performance metric score. One or more representations of the one or more sets of content item text may be displayed.

Abstract: A capacitor unit includes a bottom electrode; a raised sub-structure provided on the bottom electrode and having a plurality of trenches exposing the bottom electrode; a first capacitance conductive layer formed on a surface of the raised sub-structure and a surface of the bottom electrode, the first capacitance conductive layer having a substantially uniform thickness; a capacitance insulation layer formed on a surface of the first capacitance conductive layer and having a substantially uniform thickness; and a top electrode covering a surface of the capacitance insulation layer. A side of the top electrode abutting the capacitance insulation layer is extended along the surface of the capacitance insulation layer.

Abstract: A capacitor structure including a substrate, an insulating layer, a capacitor, a shielding layer, a first connection terminal, and a second connection terminal is disposed. The insulating layer is disposed on the substrate. The capacitor includes a first electrode layer, a second electrode layer, a dielectric layer. The first electrode layer is disposed on the insulating layer. The second electrode layer is disposed on the first electrode layer. The dielectric layer is disposed between the first electrode layer and the second electrode layer. The shielding layer is disposed in the insulating layer. The shielding layer is located between the first electrode layer and the substrate. The first connection terminal is electrically connected to the first electrode layer. The second connection terminal is electrically connected to the second electrode layer.

Abstract: A capacitor unit includes a substrate; an insulation layer formed on the substrate; a capacitor stacking structure formed on the insulation layer, and having a first bonding pad, a first conductive portion, a second bonding pad and a second conductive portion; and a first metallic wall and a second metallic wall formed on two opposite sides of the capacitor stacking structure. A capacitor integrated structure includes a wafer; a plurality of capacitor stacking structures arrayed in X-axis direction and Y-axis direction of the wafer to form a matrix on the wafer; a plurality of metallic dividers provided in the X-axis direction of the wafer between adjacent ones of the capacitor stacking structures; and a plurality of insulation dividers provided in the Y-axis direction of the wafer between adjacent ones of the capacitor stacking structures.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a first performance metric score may be determined based upon first content item text. A plurality of similarity scores associated with a plurality of sets of content item text may be determined. One or more sets of content item text may be selected from among the plurality of sets of content item text based upon the plurality of similarity scores and a plurality of performance metric scores associated with the plurality of sets of content item text. The plurality of performance metric scores may comprise one or more performance metric scores associated with the one or more sets of content item text. The one or more performance metric scores may be higher than the first performance metric score. One or more representations of the one or more sets of content item text may be displayed.

Abstract: A capacitor integrated structure, a capacitor unit and a manufacturing process thereof are provided. The manufacturing process of capacitor units includes the steps of: forming a plurality of capacitor stacking structures on a substrate having an insulation layer thereon; performing a first cut on insulation dividers provided between the adjacent capacitor stacking structures to form a plurality of recesses that expose first conductive portion and second conductive portion of each of the capacitor stacking structures; filling a metallic material in the recesses to form a plurality of metallic dividers that are electrically connected to the first conductive portion and the second conductive portion of each of the capacitor stacking structures; performing a second cut on the metallic dividers to form a plurality of independent capacitor units; and forming metallic walls on two opposite sides of each of the capacitor units, so as to provide a capacitor unit having two end electrodes.

Abstract: A capacitor structure including a substrate, a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, a third electrode, and a stress balance layer is provided. The substrate has trenches and a pillar portion located between two adjacent trenches. The first electrode is disposed on the substrate, on the pillar portion, and in the trenches. The first dielectric layer is disposed on the first electrode and in the trenches. The second electrode is disposed on the first dielectric layer and in the trenches. The second dielectric layer is disposed on the second electrode and in the trenches. The third electrode is disposed on the second dielectric layer and in the trenches. The third electrode has a groove, and the groove is located in the trench. The stress balance layer is disposed in the groove.

Abstract: A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost.

Abstract: A capacitor structure including a substrate, a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, a third electrode, and a stress balance layer is provided. The substrate has trenches and a pillar portion located between two adjacent trenches. The first electrode is disposed on the substrate, on the pillar portion, and in the trenches. The first dielectric layer is disposed on the first electrode and in the trenches. The second electrode is disposed on the first dielectric layer and in the trenches. The second dielectric layer is disposed on the second electrode and in the trenches. The third electrode is disposed on the second dielectric layer and in the trenches. The third electrode has a groove, and the groove is located in the trench. The stress balance layer is disposed in the groove.

Abstract: A microfluidic sensor chip includes a body comprising a substrate and an upper cover, and the upper cover having at least one opening, at least one microfluidic channel formed on the substrate and has a supporting surface, wherein the at least one microfluidic channel communicates with the at least one opening, and a metamaterial layer coated on the supporting surface, wherein the metamaterial layer has a plurality of regions, and each region has a corresponding resonance pattern. The present disclosure further provides a measuring system for microfluidic sensor chip includes a carrying board, a plurality of the microfluidic sensor chips, a transmitter emitting a terahertz wave corresponding to the resonance pattern of one of the microfluidic sensor chips, a receiver receiving a reflected wave corresponding to the terahertz wave, and a processor receiving the reflected wave from the processor, and determining a testing sample characteristic according to the reflected wave.

Abstract: A capacitor unit formed by a capacitor integrated structure is provided. The capacitor integrated structure is cut to form capacitor units separated from each other, and each of the capacitor units includes: a substrate; an isolation layer located on the substrate; a capacitor stacked structure located on the isolation layer, wherein the isolation layer electrically isolates the substrate from the capacitor stacked structure; and two electrode connectors located on the capacitor stacked structure and being exposed.

Abstract: A 3D cell culture gel kit and a 3D cell culture method using the same are provided. The 3D cell culture gel kit includes a gel material A, a buffer solution C, and a buffer solution D. The 3D cell culture method includes the steps of adding cells into a mixed solution containing the gel material A and setting the mixed solution at low temperature to get gel containing the cells. Then adding the buffer solution C to the gel for performing crosslinking. Next removing the buffer solution C and adding a growth medium. Let stand until the cells form spheroids in the gel. Moreover, the buffer solution D is used to dissolve the gel and the cells cultured are taken out for analysis. Thereby the 3D cell culture gel kit is convenient to use and suitable for 3D culture of a plurality of cell lines.

Abstract: The disclosure provides a calibration assembly for a scan device. The calibration assembly includes a plurality of light-permeable plates and a reflection plate. The light-permeable plates are different in size, and the light-permeable plates are arranged along thicknesses directions thereof to form a step shape. The light-permeable plates define a plurality of light-permeable areas that respectively have different numbers of layers of the light-permeable plates inversely proportional to transmittances of the light-permeable areas. The light-permeable areas are configured to be permeable to a light having a predetermined frequency. The reflection plate is disposed at a side of one of the light-permeable plates in the thickness direction thereof. The reflection plate has a plurality of first holes having different sizes, and the reflection plate is configured to block the light having the predetermined frequency. The disclosure also provides a calibration system having the calibration assembly.

Abstract: A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost.