Patents by Inventor Wei Yuan

Wei Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250132472
    Abstract: Provided is a battery insulator, a top cover assembly, and a battery. The battery insulator includes a first member and a second member. The first member includes a first main body, an end of the first main body facing towards the second member is provided with two baffles at intervals. The second member includes a second main body, and an end of the second main body facing towards the first main body is provided with a mounting plate. The mounting plate is provided with a first pole hole in a penetrating manner, the first pole hole is configured to allow a pole of a battery to pass through, the mounting plate is movably disposed between the two baffles, the mounting plate and the two baffles define an accommodation groove, and the accommodation groove is configured to accommodate a tab connected to the cell.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 24, 2025
    Inventors: Kuanjin SHU, Wei YUAN, Xu ZHENG, Xiaowu HE, Wei HE
  • Publication number: 20250132272
    Abstract: An electronic device is provided. The electronic device includes a protective layer, a chip disposed on the protective layer, a first connector electrically connected to the chip, and an antenna unit disposed on the first connector and electrically connected to the chip. The antenna unit includes a pattern layer and a covering layer disposed on the pattern layer. The pattern layer includes a first surface and the covering layer includes a second surface. The first surface is rougher than the second surface.
    Type: Application
    Filed: September 18, 2024
    Publication date: April 24, 2025
    Inventors: Jui-Jen YUEH, Wei-Yuan CHENG, Ker-Yih KAO
  • Publication number: 20250118792
    Abstract: The present invention relates to the technical field of electrochemistry, and in particular, to a structured electrode, a preparation method therefor and a use thereof. The structured electrode of the present invention comprises an electrode body, and a surface of the electrode body is provided with an etched structure; and the electrode body is of an array structure composed of three-dimensional electrode wires.
    Type: Application
    Filed: November 15, 2022
    Publication date: April 10, 2025
    Applicant: South China University of Technology
    Inventors: Wei YUAN, Yintong YE, Yang YANG, Xinzhu GAO, Chun WANG, Xiaoqing ZHANG
  • Publication number: 20250107306
    Abstract: A light emitting element package includes a first substrate, at least one light emitting element, an encapsulation layer, and a plurality of conductive pads. The first substrate has an upper surface and a lower surface opposite to each other, in which an edge of the lower surface has a notch. The at least one light emitting element is disposed on the upper surface of the first substrate, in which the light emitting element has a positive electrode and a negative electrode. The encapsulation layer covers the light emitting element. The plurality of conductive pads are disposed on the lower surface of the first substrate and electrically connected to the positive electrode and the negative electrode of the light emitting element, respectively.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Inventors: Chih-Hao LIN, Wei-Yuan MA, Jo-Hsiang CHEN
  • Patent number: 12237390
    Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes receiving a workpiece that includes a first gate structure disposed over a first active region, a second gate structure disposed over a second active region, a first gate spacer extending along a sidewall of the first gate structure and disposed at least partially over a top surface of the first active region, a second gate spacer extending along a sidewall of the second gate structure and disposed at least partially over a top surface of the second active region, and a source/drain feature. The method also includes treating a portion of the first gate spacer and a portion of the second gate spacer with a remote radical of hydrogen or oxygen, removing the treated portions, and after the removal, depositing a metal fill material over the source/drain feature.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Wei Tseng, Wei-Yuan Lu, Wei-Yang Lee, Chia-Pin Lin, Tzu-Wei Kao
  • Patent number: 12229553
    Abstract: A software developer proxy tool accesses microservice applications for a software development project by connecting the developer proxy tool to a common port on a computer network. The tool implements software and hardware to register a plurality of the microservice applications on connection ports that connect to the developer proxy tool at an address for the common port. Data requests among the microservices are handled by the developer proxy tool via the common port. The tool sequentially queries selected microservice applications on the respective connection ports to determine availability for completing a request. The tool receives responses back from microservices and directs the responses back to the requesting program. Failed requests trigger use of remote or third party microservice applications that may be available over an internet connection.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: February 18, 2025
    Assignee: Change Healthcare Holdings, LLC
    Inventors: Henry Spivey, Chun-Fu Chang, Wei-Yuan Lo
  • Patent number: 12230228
    Abstract: A light-emitting assembly includes a substrate and a plurality of light-emitting elements disposed on the substrate. The substrate includes a base material layer, a first electrical conductive layer and a protection layer in a sectional view. A thickness of the first electrical conductive layer is greater than a thickness of the protection layer. The thickness of the protection layer is greater than 0 ?m and less than 30 ?m. This disclosure can improve the non-uniform brightness issue (hotspots) or enhance the optical performance.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: February 18, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Chung-Chun Kuo, Chun-Fang Chen, Hui-Wen Su, Wei-Yuan Chen, Chung-Yu Cheng
  • Publication number: 20250056242
    Abstract: Systems and methods may use a math programming model for designing an edge cloud network. The edge cloud network design may depend on various factors, including the number of edge cloud nodes, edge cloud node location, or traffic coverage, among other things.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Applicant: AT&T Intellectual Property I, L.P.
    Inventors: Sichong Guan, Wei Yuan, Arun Jotshi, Abraham George, Carolyn Roche Johnson, Kenichi Futamura, Mohan Gawande
  • Patent number: 12223921
    Abstract: A drive method for a display panel, and a display apparatus. The drive method includes: when current original gray-scale values corresponding to sub-pixels in the same region are the same in a plurality of continuous display frames, converting the current original gray-scale values into a first target gray-scale value and a second target gray-scale value; in a current display frame of the plurality of continuous display frames, controlling a data voltage corresponding to the first target gray-scale value to be input to a first sub-pixel unit in the region, and controlling a data voltage corresponding to the second target gray-scale value to be input to a second sub-pixel unit in the region, where each of the first sub-pixel unit and the second sub-pixel unit includes at least one sub-pixel.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: February 11, 2025
    Assignees: Wuhan BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Rongcheng Liu, Hui Wang, Wei Yuan, Yanwei Lv, Shaohui Li, Jiantao Liu
  • Publication number: 20250034323
    Abstract: A polymer is a biodegradable polymer, and a constituent monomer of the polymer includes a 2-hydroxyethyl methacrylate, a lactide and a caprolactone. When an average molecular weight of the polymer is Mw, a degradation rate of the polymer on a 7th day is Dr7, and a time for the polymer to reach a 1% degradation rate is TDr1p, the specific conditions related to Mw and Dr7 or TDr1p, respectively, can be satisfied.
    Type: Application
    Filed: June 27, 2024
    Publication date: January 30, 2025
    Inventors: Wei-Yuan CHEN, Po-Tsun CHEN, Rih-Sian CHEN, Yi-Rou LU, Yu Jie HONG, Chun-Hung TENG
  • Patent number: 12206059
    Abstract: A light emitting element package includes a first substrate, at least one light emitting element, an encapsulation layer, and a plurality of conductive pads. The first substrate has an upper surface and a lower surface opposite to each other, in which an edge of the lower surface has a notch. The at least one light emitting element is disposed on the upper surface of the first substrate, in which the light emitting element has a positive electrode and a negative electrode. The encapsulation layer covers the light emitting element. The plurality of conductive pads are disposed on the lower surface of the first substrate and electrically connected to the positive electrode and the negative electrode of the light emitting element, respectively.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: January 21, 2025
    Assignee: Lextar Electronics Corporation
    Inventors: Chih-Hao Lin, Wei-Yuan Ma, Jo-Hsiang Chen
  • Publication number: 20250022854
    Abstract: Provide a micro-light-emitting package includes a first substrate, a plurality of micro-light-emitting diodes (micro-LEDs), a transparent protective layer, and a plurality of conductive pads. The first substrate has an upper surface and a lower surface opposite to each other. The micro-LEDs are disposed on the upper surface of the first substrate. The micro-LEDs have a first electrode and a second electrode electrically opposite to the first electrode. The transparent protective layer covers the micro-LEDs. The plurality of conductive pads are disposed on the lower surface of the first substrate. The conductive pads include a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad. The first conductive pad, the second conductive pad, the third conductive pad respectively electrically connected to the corresponding first electrode of the micro-LEDs. The fourth conductive pad is commonly electrically connected to the second electrode of the plurality of micro-LEDs.
    Type: Application
    Filed: June 18, 2024
    Publication date: January 16, 2025
    Inventors: Chih-Hao LIN, Po-Han WU, Tsung-Hao SU, Wei-Yuan MA
  • Publication number: 20250021732
    Abstract: A selecting method of a non-simplified region of a 3D model of a multilayer metal circuit structure is used for selecting a first non-simplified region in a complete 3D model of a layout design of a multilayer metal circuit structure. The complete 3D model contains multiple layout layers. The electing method of the first non-simplified region includes at least one of first to fourth selecting modes. Through the selecting method of the non-simplified region of the present invention, the entire complete 3D can be effectively simplified in a programmed manner, shortening the overall electrical simulation time.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 16, 2025
    Inventors: Ji-Min LIN, Wei-Yuan LIN
  • Patent number: 12173135
    Abstract: A plasticizer, which is biodegradable, has a molecule including a central structure, at least two connecting structures and at least one side-chain structure. The central structure includes at least one of a benzene derivative and at least one amino acid. The connecting structures are respectively connected to the central structure, wherein the connecting structures include a first connecting structure and a second connecting structure. The first connecting structure is an amine group, and the second connecting structure is a carboxyl group. The side-chain structure is a chain of multiple carbon atoms, and the side-chain structure is connected to at least one of the first connecting structure and the second connecting structure. An amide bond is formed as the side-chain structure connected to the amine group, and an ester bond is formed as the side-chain structure connected to the carboxyl group.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: December 24, 2024
    Assignee: LARGAN MEDICAL CO., LTD.
    Inventors: Wei-Yuan Chen, Tzu-Rong Lu, Yi-Ling Chen, Chun-Hung Teng
  • Patent number: 12175172
    Abstract: A computer-implemented method for meshing a model of a physical electro-magnetic assembly is disclosed. The method includes separating the base mesh of the model into two domains and freezing the boundary between these domains. Each domain is then sent for mesh refinement by separate computer processors. Each computer processor generates a refined mesh of the respective domain without communication between processors. Two-way boundary mesh mapping is then performed, resulting in a global conformal mesh. Surface recovery and identity assignment are then performed by separate computer processors in parallel for each domain, without communication between processors. Related apparatus, systems, techniques, methods and articles are also described.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: December 24, 2024
    Assignee: ANSYS, INC.
    Inventors: Wei Yuan, Yunjun Wu
  • Patent number: 12167250
    Abstract: Systems and methods may use a math programming model for designing an edge cloud network. The edge cloud network design may depend on various factors, including the number of edge cloud nodes, edge cloud node location, or traffic coverage, among other things.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: December 10, 2024
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Sichong Guan, Wei Yuan, Arun Jotshi, Abraham George, Carolyn Roche Johnson, Kenichi Futamura, Mohan Gawande
  • Publication number: 20240404904
    Abstract: An electronic device includes an electronic component including a chip and a protective layer disposed on the active surface of the chip; an encapsulation layer surrounding the electronic component; and a circuit structure contacting the first surface of the encapsulation layer and electrically connecting the electronic component. The protective layer has a second surface away from the active surface, and a first step difference between the first surface and the second surface is between 1 and 10 ?m.
    Type: Application
    Filed: May 6, 2024
    Publication date: December 5, 2024
    Inventors: Ker-Yih KAO, Wei-Yuan CHENG, Ju-Li WANG
  • Publication number: 20240395811
    Abstract: In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yuan LU, Sai-Hooi YEONG
  • Patent number: 12154902
    Abstract: In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yuan Lu, Sai-Hooi Yeong
  • Publication number: 20240379762
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang