Patents by Inventor Wei Yuan

Wei Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220302299
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Publication number: 20220301492
    Abstract: The pixel driving circuit includes a current control circuit and a gating circuit. The current control circuit is configured to transmit a driving current signal to an element to be driven. The gating circuit is configured to transmit a second voltage signal from a second voltage signal terminal to the element to be driven such that the element to be driven continuously emits light or transmit a third voltage signal from a third voltage signal terminal to the element to be driven such that the element to be driven intermittently emits light, under the control of a scan signal from a scan signal terminal, a reset signal from a reset signal terminal and a second data signal from a second data signal terminal.
    Type: Application
    Filed: November 19, 2021
    Publication date: September 22, 2022
    Inventors: Lijun YUAN, Can ZHANG, Ning CONG, Wei LI, Can WANG, Jinfei NIU, Jingjing ZHANG, Minghua XUAN
  • Publication number: 20220301849
    Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventors: Wei-Lin CHANG, Chih-Chien WANG, Chihy-Yuan CHENG, Sz-Fan CHEN, Chien-Hung LIN, Chun-Chang CHEN, Ching-Sen KUO, Feng-Jia SHIU
  • Patent number: 11451276
    Abstract: A method and apparatus for generating and utilizing spreading sequence codebooks for a symbol-level sequence spreading is disclosed. In one embodiment, a method performed by a wireless communication device, comprising: receiving a first number from a wireless communication node; selecting a first spreading sequence codebook from at least one spreading sequence codebook; selecting a first spreading sequence from the first spreading sequence codebook according to the first number; and spreading data symbols according to the first spreading sequence, wherein the at least one spreading sequence codebook each comprises a plurality of spreading sequences configured based on one entry of a first sequence set after cyclic shifting operation, wherein the first sequence set before cyclic shifting operation is configured based on a second sequence set.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: September 20, 2022
    Assignee: ZTE Corporation
    Inventors: Sha Wang, Yifei Yuan, Li Tian, Zhifeng Yuan, Wei Cao
  • Patent number: 11450763
    Abstract: Provided is an IGBT power device. The device includes: a p-type collector region; an n-type drift region located above the p-type collector region; multiple first grooves, where a second groove is provided below each of the multiple first grooves; a gate structure located in the first groove and the second groove; a p-type body region located between two adjacent first grooves; an n-type emitter region located in the p-type body region; and an n-type hole charge blocking region located between two adjacent second grooves.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: September 20, 2022
    Assignee: Suzhou Oriental Semiconductor Co., Ltd.
    Inventors: Wei Liu, Lei Liu, Zhendong Mao, Yuanlin Yuan
  • Patent number: 11450605
    Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Yuan Chen, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei-Min Chan
  • Patent number: 11450661
    Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Hsu, Yi-Tang Lin, Clement Hsingjen Wann, Chih-Sheng Chang, Wei-Chun Tsai, Jyh-Cherng Sheu, Chi-Yuan Shih
  • Publication number: 20220287736
    Abstract: A reusable ultrasonic scalpel comprising a handle assembly and an ultrasonic waveguide extended to the distal end transmitting ultrasonic mechanical energy. Outside the ultrasonic waveguide is a sheath assembly, and the sheath assembly is detachably connected to the handle assembly by a quick connecting mechanism. The beneficial effects are mainly reflected on: reliable installation, easy to disassemble, easy to clean and disinfect. The sheath assembly serving as a consumable may be quickly replaced, while the remaining parts may be reused, and may undergo cleaning and high temperature steam sterilization.
    Type: Application
    Filed: April 13, 2020
    Publication date: September 15, 2022
    Inventors: Ke LIU, Xiaohe YUAN, Zhenzhong LIU, Zhongyu YAN, Wei LUO
  • Publication number: 20220292244
    Abstract: One aspect of this description relates to a method for operating an integrated circuit (IC) manufacturing system. The method includes placing a first nano-sheet structure within a IC layout diagram. The first nano-sheet structure has a first width. The method includes abutting a second nano-sheet structure with the first nano-sheet structure. The second nano-sheet structure has a second width. The second width is less than the first width. The method includes generating and storing the IC layout diagram in a storage device.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Wei-Cheng Lin, Yan-Hao Chen, Jiann-Tyng Tzeng, Lipen Yuan, Hui-Zhong Zhuang, Yu-Xuan Huang
  • Publication number: 20220293578
    Abstract: A device includes a substrate having a first surface and a second surface opposite to the first surface; a thin-film transistor array disposed on the first surface, including a plurality of transistors; a plurality of diodes disposed on the thin-film transistor array; a plurality of conductive structures penetrating through the substrate from the first surface to the second surface, wherein the plurality of conductive structures are corresponding to the plurality of diodes and electrically connected to the plurality of diodes; a driver unit disposed on the second surface of the substrate; a patterned conductive layer disposed between the substrate and the driver unit; a protection layer disposed on the patterned conductive layer, wherein the protection layer has an opening that exposes the patterned conductive layer; and a conductive material disposed in the opening.
    Type: Application
    Filed: May 30, 2022
    Publication date: September 15, 2022
    Inventors: Wei-Cheng CHU, Ming-Fu JIANG, Chia-Cheng LIU, Chih-Yuan LEE
  • Publication number: 20220294896
    Abstract: Embodiments of this application disclose a call method and an apparatus. In the call method, when a user does not actively select an audio device as a voice pickup device and a voice play device, after establishing a call connection to another electronic device, an electronic device selects, from available audio devices, an audio device that meets a user expectation as the voice pickup device and the voice play device. According to technical solutions provided in the embodiments of this application, user experience in a call process can be improved.
    Type: Application
    Filed: August 6, 2020
    Publication date: September 15, 2022
    Inventors: Fusheng LI, Shengfeng ZHOU, Yi YU, Wei YUAN
  • Patent number: 11445277
    Abstract: Provided are a link establishment method and apparatus and a computer-readable storage medium. The link establishment method includes: exchanging optical link auto-negotiation information with a terminal device through an optical link auto-negotiation channel; and in a case where exchanging the optical link auto-negotiation information is finished, establishing at least one of a traffic data channel or an optical link auto-negotiation channel; where the optical link auto-negotiation channel is independent of the traffic data channel or the optical link auto-negotiation channel; and the optical link auto-negotiation information includes at least one of information about an operating wavelength channel of the terminal device, an enabled or disabled state of forward error correction with the terminal device, a forward error correction type with the terminal device, or an operating mode of the auxiliary management channel.
    Type: Grant
    Filed: October 12, 2019
    Date of Patent: September 13, 2022
    Assignee: ZTE CORPORATION
    Inventors: Wei Yang, Bo Yang, Huannan Ma, Xiangrong Chen, Yufeng Li, Liquan Yuan
  • Patent number: 11444028
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Publication number: 20220285486
    Abstract: Provided is a semiconductor super junction power device. The semiconductor super junction power device includes an MOSFET cell array composed of multiple super junction MOSFET cells. Each of multiple MOSFET cells includes a p-type body region located at the top of an n-type drift region, a p-type columnar doping region located below the p-type body region, an n-type source region located in the p-type body region, a gate dielectric layer located above the p-type body region, a gate electrode located above the p-type body region, an n-type floating gate located above the p-type body region and an opening located in the gate dielectric layer, where in a lateral direction, the gate electrode is located on one side close to the n-type source region; an opening located in the gate dielectric layer, where the n-type floating gate contacts the p-type body region through the opening to form a p-n junction diode.
    Type: Application
    Filed: December 5, 2019
    Publication date: September 8, 2022
    Inventors: Yi GONG, Wei LIU, Yuanlin YUAN, Lei LIU, Rui WANG
  • Publication number: 20220285544
    Abstract: Provided is a semiconductor power device. The device includes: at least one p-type body region located on the top of an n-type drift region, a first n-type source region and a second n-type source region located within the p-type body region, a first gate structure configured to control a first current channel between the first n-type source region and the n-type drift region to be turned on or off; and a second gate structure configured to control a second current channel between the second n-type source region and the n-type drift region to be turned on or off. The second gate structure is recessed in the n-type drift region.
    Type: Application
    Filed: December 5, 2019
    Publication date: September 8, 2022
    Inventors: Yi GONG, Zhendong MAO, Wei LIU, Lei LIU, Yuanlin YUAN
  • Publication number: 20220285536
    Abstract: Provided is an insulated gate bipolar transistor (IGBT) device. The IGBT device includes p-type body regions located on a top of an n-type drift region, a first n-type emitter region located within the p-type body region; a first gate structure located over the p-type body region, where the first gate structure includes a first gate dielectric layer, a first gate and an n-type floating gate which are located above the first gate dielectric layer, where the n-type floating gate is located on a side close to the n-type drift region in a lateral direction; an insulating dielectric layer located between the n-type floating gate and the first gate; and one opening in the first gate dielectric layer. The n-type floating gate is in contact with the p-type body region to form a p-n junction diode through the one opening.
    Type: Application
    Filed: November 27, 2019
    Publication date: September 8, 2022
    Inventors: Yi GONG, Rui WANG, Wei LIU, Yuanlin YUAN, Xin WANG
  • Publication number: 20220285294
    Abstract: An embodiment of the disclosure provides a package device including a redistribution layer, an integrated passive device layer, a first port, and a second port. The integrated passive device layer contacts the redistribution layer. The integrated passive device layer has at least one capacitor. The at least one capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is provided opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance.
    Type: Application
    Filed: October 7, 2021
    Publication date: September 8, 2022
    Applicant: Innolux Corporation
    Inventors: Yeong-E Chen, Wei-Hsuan Chen, Chun-Yuan Huang
  • Publication number: 20220285535
    Abstract: Provided is an insulated gate bipolar transistor power device. The IGBT power device includes a gate dielectric layer located above the two p-type body regions and the n-type drift region between the two p-type body regions, an n-type floating gate located above the gate dielectric layer; a gate located above the gate dielectric layer and the n-type floating gate; an insulating dielectric layer between the gate and the n-type floating gate; a first opening located in the gate dielectric layer, where the n-type floating gate is in contact with one of the two p-type body regions through the first opening to form a p-n junction diode; and a second opening located in the gate dielectric layer, where the n-type floating gate is in contact with the other of the two p-type body regions through the second opening to form the p-n junction diode.
    Type: Application
    Filed: December 6, 2019
    Publication date: September 8, 2022
    Inventors: Yi GONG, Lei LIU, Wei LIU, Yuanlin YUAN, Xin WANG
  • Patent number: 11437239
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming a first spacer and a second spacer respectively over opposite inner walls of the trench. The first spacer and the second spacer are spaced apart from each other. The method includes removing a first portion of the first spacer to form a first gap in the first spacer, wherein a first part and a second part of the first spacer are spaced apart by the first gap, and the first gap communicates with the trench. The method includes forming a filling layer into the trench and the first gap to cover the first spacer and the second spacer. The filling layer, the first spacer, and the second spacer together form a strip structure. The method includes removing the first layer.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Ming Lai, Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu
  • Publication number: 20220275282
    Abstract: A method and apparatus for hydrocracking mineralized refuse pyrolysis oil. The method may use the following steps: (a) crushing and pyrolyzing mineralized refuse to obtain arene and alkane precursor biomass oil; (b) hydrogenating the arene and alkane precursor biomass oil obtained in step (a), and separating the obtained hydrocrackate to obtain arene and alkane; and (c) purifying, recovering and optimizing the arene and alkane obtained in step (b), and performing deep processing to produce naphtha, jet fuel, light diesel oil, and heavy diesel oil.
    Type: Application
    Filed: June 16, 2020
    Publication date: September 1, 2022
    Applicant: East China University of Science and Technology
    Inventors: Yulong CHANG, Hualin WANG, Xia JIANG, Jianping LI, Jingyi ZHU, Pengbo FU, Wei YUAN