Abstract: A polymer is a biodegradable polymer, and a constituent monomer of the polymer includes a 2-hydroxyethyl methacrylate, a lactide and a caprolactone. When an average molecular weight of the polymer is Mw, a degradation rate of the polymer on a 7th day is Dr7, and a time for the polymer to reach a 1% degradation rate is TDr1p, the specific conditions related to Mw and Dr7 or TDr1p, respectively, can be satisfied.

Abstract: A light emitting element package includes a first substrate, at least one light emitting element, an encapsulation layer, and a plurality of conductive pads. The first substrate has an upper surface and a lower surface opposite to each other, in which an edge of the lower surface has a notch. The at least one light emitting element is disposed on the upper surface of the first substrate, in which the light emitting element has a positive electrode and a negative electrode. The encapsulation layer covers the light emitting element. The plurality of conductive pads are disposed on the lower surface of the first substrate and electrically connected to the positive electrode and the negative electrode of the light emitting element, respectively.

Abstract: A selecting method of a non-simplified region of a 3D model of a multilayer metal circuit structure is used for selecting a first non-simplified region in a complete 3D model of a layout design of a multilayer metal circuit structure. The complete 3D model contains multiple layout layers. The electing method of the first non-simplified region includes at least one of first to fourth selecting modes. Through the selecting method of the non-simplified region of the present invention, the entire complete 3D can be effectively simplified in a programmed manner, shortening the overall electrical simulation time.

Abstract: Provide a micro-light-emitting package includes a first substrate, a plurality of micro-light-emitting diodes (micro-LEDs), a transparent protective layer, and a plurality of conductive pads. The first substrate has an upper surface and a lower surface opposite to each other. The micro-LEDs are disposed on the upper surface of the first substrate. The micro-LEDs have a first electrode and a second electrode electrically opposite to the first electrode. The transparent protective layer covers the micro-LEDs. The plurality of conductive pads are disposed on the lower surface of the first substrate. The conductive pads include a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad. The first conductive pad, the second conductive pad, the third conductive pad respectively electrically connected to the corresponding first electrode of the micro-LEDs. The fourth conductive pad is commonly electrically connected to the second electrode of the plurality of micro-LEDs.

Abstract: A plasticizer, which is biodegradable, has a molecule including a central structure, at least two connecting structures and at least one side-chain structure. The central structure includes at least one of a benzene derivative and at least one amino acid. The connecting structures are respectively connected to the central structure, wherein the connecting structures include a first connecting structure and a second connecting structure. The first connecting structure is an amine group, and the second connecting structure is a carboxyl group. The side-chain structure is a chain of multiple carbon atoms, and the side-chain structure is connected to at least one of the first connecting structure and the second connecting structure. An amide bond is formed as the side-chain structure connected to the amine group, and an ester bond is formed as the side-chain structure connected to the carboxyl group.

Abstract: A computer-implemented method for meshing a model of a physical electro-magnetic assembly is disclosed. The method includes separating the base mesh of the model into two domains and freezing the boundary between these domains. Each domain is then sent for mesh refinement by separate computer processors. Each computer processor generates a refined mesh of the respective domain without communication between processors. Two-way boundary mesh mapping is then performed, resulting in a global conformal mesh. Surface recovery and identity assignment are then performed by separate computer processors in parallel for each domain, without communication between processors. Related apparatus, systems, techniques, methods and articles are also described.

Abstract: Systems and methods may use a math programming model for designing an edge cloud network. The edge cloud network design may depend on various factors, including the number of edge cloud nodes, edge cloud node location, or traffic coverage, among other things.

Abstract: An electronic device includes an electronic component including a chip and a protective layer disposed on the active surface of the chip; an encapsulation layer surrounding the electronic component; and a circuit structure contacting the first surface of the encapsulation layer and electrically connecting the electronic component. The protective layer has a second surface away from the active surface, and a first step difference between the first surface and the second surface is between 1 and 10 ?m.

Abstract: In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.

Abstract: In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

Abstract: The present disclosure provides a voice interaction system, a voice interaction method, and a smart device. The system includes: a voice interaction unit, a photoelectric sensing unit, and an instruction control unit configured to determine whether the voice interaction unit is in an on state, determine, when the voice interaction unit is in the on state, whether the voice interaction unit receives a target voice instruction within a predetermined time; control, when the target voice instruction is received within the predetermined time, a smart device to perform an action corresponding to the target voice instruction according to the target voice instruction of the user received and identified by the voice interaction unit; and send, when the voice instruction is not received within the predetermined time, a standby instruction to the voice interaction unit.

Abstract: An electronic device includes a substrate, a circuit layer, at least one electronic unit, a stress adjustment layer, and a buffer layer. The substrate has a first surface and a second surface opposite to each other and at least one side connected to the first surface and the second surface. The circuit layer is disposed on the first surface of the substrate. The at least one electronic unit is electronically connected to the circuit layer. The stress adjustment layer is disposed on the second surface of the substrate. The buffer layer surrounds the substrate, wherein the stress adjustment layer is located between the substrate and the buffer layer, and the buffer layer is in contact with the at least one side of the substrate.

Abstract: A micro light-emitting diode package structure and a forming method thereof are provided. The micro light-emitting diode package structure includes micro light-emitting diode dies, a light-transmitting layer, a first insulating layer, redistribution layers, and conductive elements. The micro light-emitting diode dies are disposed side by side and each includes an electrode surface, a light-emitting surface, and side surfaces. The electrode surface and the light-emitting surface are opposite to each other, and the side surfaces are between them. The light-transmitting layer covers the light-emitting surface and the side surfaces. The first insulating layer is under the micro light-emitting diode dies and in direct contact with the electrode surface. The redistribution layers are disposed under the first insulating layer and pass through the first insulating layer to electrically connect the electrode surface.

Abstract: A polymer, which is a composition of a battery, includes a polyester. The polyester is polymerized by at least two monomers, wherein each of the at least two monomers is selected from a group consisting of a carbonate ester and a polyol. The polyester can further include an end-capped polycarbonate ester, and the end-capped polycarbonate ester includes an inert group on an end thereof.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: A polymer has a degradability and includes a monomer. The monomer of the polymer includes a benzene derivative, a lactide and a caprolactone. A ratio of the benzene derivative in the polymer is smaller than a ratio of the lactide in the polymer. The ratio of the benzene derivative in the polymer is smaller than a ratio of the caprolactone in the polymer.

Abstract: A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.