Patents by Inventor Wei ZHE

Wei ZHE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111597
    Abstract: A present invention embodiment requests resources for a set of tasks from different resource providers. The set of tasks includes first tasks and second tasks of longer duration than the first tasks. The resources are revocable by the different resource providers based on processing demand. Performance of the first tasks is initiated on the resources, and stable resources are identified based on revocation of the resources during performance of the first tasks. Performance of the second tasks are initiated on the identified stable resources. Requests for the resources to the different resource providers are adjusted based on resource provider information collected in response to completion of the set of tasks.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Guang Han Sui, Wei Ge, Lan Zhe Liu, Guo Liang Wang
  • Patent number: 11923454
    Abstract: An epitaxial structure includes a substrate, a lower super-lattice laminate, a middle super-lattice laminate, an upper super-lattice laminate and a channel layer. The lower super-lattice laminate includes a plurality of first lower film layers and a plurality of second lower film layers stacked alternately. The first lower film layer includes aluminum nitride. The second lower film layer includes aluminum gallium nitride. The middle super-lattice laminate includes a plurality of first middle film layers and a plurality of second middle film layers stacked alternately. The first middle film layer includes aluminum nitride. The second middle film layer includes gallium nitride doped with a doping material. The upper super-lattice laminate includes a plurality of first upper film layers and a plurality of second upper film layers stacked alternately. The first upper film layer includes gallium nitride doped with the doping material. The second upper film layer includes gallium nitride.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 5, 2024
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Wei-Jie Sie, Jia-Zhe Liu, Ying-Ru Shih
  • Patent number: 11882871
    Abstract: A detachable atomizing device and a container thereof are provided. The container is detachably assembled to an atomizing assembly. The container includes a cup and a flexible film. The cup has an opening arranged at an end thereof, the flexible film covers the opening of the cup, and the flexible film has a tension region and an outer ring-shaped region that surrounds the tension region. The tension region has a plurality of atomizing holes having an average diameter within a range of 1 ?m to 20 ?m, and the outer ring-shaped region is attached to the cup. When the cup is assembled to the atomizing assembly, a tension value of the tension region of the flexible film is increased from an initial tension value to an atomizing tension value by being pressed from the atomizing assembly, and the atomizing holes of the tension region are configured to allow liquid to pass there-through and to be formed as aerosol mist having an average atomized particle diameter less than a predetermined value.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 30, 2024
    Assignee: MICROBASE TECHNOLOGY CORP.
    Inventors: Chih-Wei Lu, Chen-Hsiang Sang, Liang-Rern Kung, Wei-Zhe Cai, Jo-Ling Wu, Shu-Pin Hsieh
  • Publication number: 20230304335
    Abstract: A device with lock function includes a casing, a lock member, a cover and a shielding member. The lock member is rotatably disposed in the casing. The lock member includes a first engaging portion. The cover is disposed on the casing. The cover includes a second engaging portion. The shielding member drives the lock member to engage the first engaging portion with the second engaging portion to lock the cover.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 28, 2023
    Applicant: Wistron Corporation
    Inventor: Wei-Zhe Hong
  • Patent number: 11366162
    Abstract: A scan output flip-flop includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal to serve as an input signal. The control circuit is controlled by a first clock signal and a second clock signal to generate a first control signal and a second control signal according to the input signal. The scan-out stage circuit receives only one of the first control signal and the second control signal, and is controlled by the first test enable signal and a second test enable signal to generate a scan-out signal.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: June 21, 2022
    Assignee: MEDIATEK INC.
    Inventors: Wei-Zhe Wong, Heng-Liang Huang
  • Patent number: 11198665
    Abstract: A (Z)-solanone has the steric formula of: or with the name of (S,Z)-5-isopropyl-8-methyl-6,8-diene-2-one or (R,Z)-5-isopropyl-8-methyl-6,8-diene-2-one. A process for the preparation of the (Z)-type solanone and the use thereof in flavoring of cigarette shred are further disclosed. The process includes the following steps: (1) reacting isopentanal and methyl vinyl ketone, under the action of a catalyst and a co-catalyst, to give (S)-2-isopropyl-5-carbonylhexanal or (R)-2-isopropyl-5-carbonylhexanal; (2) reacting the (S)-2-isopropyl-5-carbonylhexanal or the (R)-2-isopropyl-5-carbonylhexanal obtained in step (1) with (iodomethyl)triphenylphosphonium iodide, to give (S,Z)-7-iodo-5-isopropyl-6-ene-2-one or (R,Z)-7-iodo-5-isopropyl-6-ene-2-one; and (3) reacting the (S,Z)-7-iodo-5-isopropyl-6-ene-2-one or the (R,Z)-7-iodo-5-isopropyl-6-ene-2-one obtained in step (2) with pinacol isopropenylborate in the presence of a catalyst to give the (Z)-solanone.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: December 14, 2021
    Assignee: CHINA TOBACCO YUNNAN INDUSTRIAL CO., LTD
    Inventors: Sheng Lei, Zhihua Liu, Kai Wang, Zhenjie Li, Deshou Mao, Kunmiao Wang, Li Gao, Lei Fu, Yipeng Zhang, Wei Zhe, Ying Yang, Qianghui Zhou
  • Publication number: 20210380517
    Abstract: A (Z)-solanone has the steric formula of: with the name of (S,Z)-5-isopropyl-8-methyl-6,8-diene-2-one or (R,Z)-5-isopropyl-8-methyl-6,8-diene-2-one. A process for the preparation of the (Z)-type solanone and the use thereof in flavoring of cigarette shred are further disclosed. The process includes the following steps: (1) reacting isopentanal and methyl vinyl ketone, under the action of a catalyst and a co-catalyst, to give (S)-2-isopropyl-5-carbonylhexanal or (R)-2-isopropyl-5-carbonylhexanal; (2) reacting the (S)-2-isopropyl-5-carbonylhexanal or the (R)-2-isopropyl-5-carbonylhexanal obtained in step (1) with (iodomethyl)triphenylphosphonium iodide, to give (S,Z)-7-iodo-5-isopropyl-6-ene-2-one or (R,Z)-7-iodo-5-isopropyl-6-ene-2-one; and (3) reacting the (S,Z)-7-iodo-5-isopropyl-6-ene-2-one or the (R,Z)-7-iodo-5-isopropyl-6-ene-2-one obtained in step (2) with pinacol isopropenylborate in the presence of a catalyst to give the (Z)-solanone.
    Type: Application
    Filed: June 1, 2020
    Publication date: December 9, 2021
    Applicant: CHINA TOBACCO YUNNAN INDUSTRIAL CO., LTD
    Inventors: Sheng LEI, Zhihua LIU, Kai WANG, Zhenjie LI, Deshou MAO, Kunmiao WANG, Li GAO, Lei FU, Yipeng ZHANG, Wei ZHE, Ying YANG, Qianghui ZHOU
  • Publication number: 20210325457
    Abstract: A scan output flip-flop includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal to serve as an input signal. The control circuit is controlled by a first clock signal and a second clock signal to generate a first control signal and a second control signal according to the input signal. The scan-out stage circuit receives only one of the first control signal and the second control signal, and is controlled by the first test enable signal and a second test enable signal to generate a scan-out signal.
    Type: Application
    Filed: March 11, 2021
    Publication date: October 21, 2021
    Inventors: Wei-Zhe Wong, Heng-Liang Huang
  • Patent number: 11087520
    Abstract: An avatar facial expression generating system and a method of avatar facial expression generation are provided. In the method, user data relating to sensing result of a user is obtained. A first and a second emotional configurations are determined. The first and second emotional configuration maintain during a first and a second duration, respectively. A transition emotional configuration is determined based on the first emotional configuration and the second emotional configuration, in which the transition emotional configuration maintains during a third duration. Facial expressions of an avatar are generated based on the first emotional configuration, the transition emotional configuration, and the second emotional configuration, respectively. The third duration exists between the first duration and the second duration. Accordingly, a normal facial expression on an avatar would be presented while encountering the emotion transformation.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: August 10, 2021
    Assignee: XRSPACE CO., LTD.
    Inventors: Wei-Zhe Hong, Ming-Yang Kung, Ting-Chieh Lin, Feng-Seng Chu
  • Patent number: 11056392
    Abstract: A method for forming a FinFET device is described. The method includes the following steps. A substrate is patterned to form fins. Dummy gate stack is formed on the substrate and over the fins, wherein the dummy gate stack may be formed by the following steps: a dummy layer is formed; a first etching step is performed on the dummy layer with a bromine containing etching gas to form a dummy strip; a second etching step is performed on the dummy strip with a chlorine containing etching gas to form the dummy gate stack. The dummy gate stack is replaced with a gate stack.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chien Li, Wei-Shuo Ho, Huang-Chao Chang, Wei-Zhe Jhang
  • Publication number: 20210134040
    Abstract: An avatar motion generating method and a head mounted display system are provided. In the method, an input event is received, and the input event is related to sensing result of a user. First avatar motion is generated based on one of predefined motion data, motion sensing data and a combination thereof at the first period of time. Second avatar motion is generated based on another of the predefined motion data, the motion sensing data and the combination thereof at the second period of time. Accordingly, the motion of the avatar could be smooth and natural.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Applicant: XRSPACE CO., LTD.
    Inventors: Wei-Zhe Hong, Pei-Wen Hsieh
  • Patent number: 10997766
    Abstract: An avatar motion generating method and a head mounted display system are provided. In the method, an input event is received, and the input event is related to sensing result of a user. First avatar motion is generated based on one of predefined motion data, motion sensing data and a combination thereof at the first period of time. Second avatar motion is generated based on another of the predefined motion data, the motion sensing data and the combination thereof at the second period of time. Accordingly, the motion of the avatar could be smooth and natural.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 4, 2021
    Assignee: XRSPACE CO., LTD.
    Inventors: Wei-Zhe Hong, Pei-Wen Hsieh
  • Publication number: 20210094059
    Abstract: A detachable atomizing device and a container thereof are provided. The container is detachably assembled to an atomizing assembly. The container includes a cup and a flexible film. The cup has an opening arranged at an end thereof, the flexible film covers the opening of the cup, and the flexible film has a tension region and an outer ring-shaped region that surrounds the tension region. The tension region has a plurality of atomizing holes having an average diameter within a range of 1 ?m to 20 ?m, and the outer ring-shaped region is attached to the cup. When the cup is assembled to the atomizing assembly, a tension value of the tension region of the flexible film is increased from an initial tension value to an atomizing tension value by being pressed from the atomizing assembly, and the atomizing holes of the tension region are configured to allow liquid to pass there-through and to be formed as aerosol mist having an average atomized particle diameter less than a predetermined value.
    Type: Application
    Filed: April 10, 2019
    Publication date: April 1, 2021
    Inventors: CHIH-WEI LU, CHEN-HSIANG SANG, LIANG-RERN KUNG, WEI-ZHE CAI, JO-LING WU, SHU-PIN HSIEH
  • Patent number: 10685728
    Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: June 16, 2020
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Zhe Wong, Ching-Sung Yang, Ching-Hsiang Hsu
  • Publication number: 20200090394
    Abstract: An avatar facial expression generating system and a method of avatar facial expression generation are provided. In the method, user data relating to sensing result of a user is obtained. A first and a second emotional configurations are determined. The first and second emotional configuration maintain during a first and a second duration, respectively. A transition emotional configuration is determined based on the first emotional configuration and the second emotional configuration, in which the transition emotional configuration maintains during a third duration. Facial expressions of an avatar are generated based on the first emotional configuration, the transition emotional configuration, and the second emotional configuration, respectively. The third duration exists between the first duration and the second duration. Accordingly, a normal facial expression on an avatar would be presented while encountering the emotion transformation.
    Type: Application
    Filed: October 17, 2019
    Publication date: March 19, 2020
    Applicant: XRSPACE CO., LTD.
    Inventors: Wei-Zhe Hong, Ming-Yang Kung, Ting-Chieh Lin, Feng-Seng Chu
  • Patent number: 10476680
    Abstract: An electronic device having anti-cloning function includes a first critical integrated circuit, which further includes a first security function block configured to authenticate an identity of a second critical integrated circuit in communication with the first critical integrated circuit, wherein the first security function block authenticates the identity of the second critical integrated circuit according to a chip identity of the second critical integrated circuit created using a non-volatile memory (NVM) physically unclonable function (PUF).
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: November 12, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Zhe Wong, Ching-Sung Yang
  • Publication number: 20190304842
    Abstract: A method for forming a FinFET device is described. The method includes the following steps. A substrate is patterned to form fins. Dummy gate stack is formed on the substrate and over the fins, wherein the dummy gate stack may be formed by the following steps: a dummy layer is formed; a first etching step is performed on the dummy layer with a bromine containing etching gas to form a dummy strip; a second etching step is performed on the dummy strip with a chlorine containing etching gas to form the dummy gate stack. The dummy gate stack is replaced with a gate stack.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chien Li, Wei-Shuo Ho, Huang-Chao Chang, Wei-Zhe Jhang
  • Patent number: 10309807
    Abstract: The present invention relates to resolver calibration for permanent magnet synchronous motor. According to embodiments of the present invention, the high frequency rotating voltage vector is generated and injected into a resolver associated with a permanent magnet synchronous motor (PMSM). Due to the saliency effect, when a reference point is detected in a phase current, the rotor position of the PMSM is known. At this point, by acquiring the resolver position, the resolver offset may be accurately determined for calibration. According to embodiments of the present invention, the resolver offset may be accurately determined and calibrated without increasing device dimension and cost. Respective methods, apparatuses, systems, and computer products are disclosed.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: June 4, 2019
    Assignee: Infineon Technologies AG
    Inventor: Wei Zhe Qian
  • Publication number: 20190096496
    Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.
    Type: Application
    Filed: November 23, 2018
    Publication date: March 28, 2019
    Applicant: eMemory Technology Inc.
    Inventors: Wei-Zhe Wong, Ching-Sung Yang, Ching-Hsiang Hsu
  • Publication number: 20190096497
    Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.
    Type: Application
    Filed: November 23, 2018
    Publication date: March 28, 2019
    Applicant: eMemory Technology Inc.
    Inventors: Wei-Zhe Wong, Ching-Sung Yang, Ching-Hsiang Hsu