Abstract: The present invention relates to resolver calibration for permanent magnet synchronous motor. According to embodiments of the present invention, the high frequency rotating voltage vector is generated and injected into a resolver associated with a permanent magnet synchronous motor (PMSM). Due to the saliency effect, when a reference point is detected in a phase current, the rotor position of the PMSM is known. At this point, by acquiring the resolver position, the resolver offset may be accurately determined for calibration. According to embodiments of the present invention, the resolver offset may be accurately determined and calibrated without increasing device dimension and cost. Respective methods, apparatuses, systems, and computer products are disclosed.

Abstract: A plasmon resonance sensing system includes a light source, a waveguide component and a photon detector. The light source provides an incident light. The waveguide component has a tubular internal wall and a noble metal nanoparticle layer disposed on the tubular internal wall and contacted with a desired testing matter. The waveguide component is made of a light transmitting material for guiding the incident light to have an interaction with the noble metal nanoparticle layer. The photon detector detects an emergent light exiting the waveguide component after the interaction of the noble metal nanoparticle layer with the desired testing matter. The system further includes a first optical fiber installed between the light source and the waveguide component for transmitting the incident light to the waveguide component, a lens and a second optical fiber. The lens collects and transmits the emergent light to the photon detector through the second optical fiber.

Abstract: A method for high dynamic range imaging includes the steps of arranging at least two cameras parallel and meanwhile capturing a plurality of images of one scene with different exposures by the at least two cameras; adjusting the captured images for the same exposure thereof subject to the response functions of the cameras respectively and then defining a plurality of characteristic spots in each of the images; combining the characteristic spots corresponding to the images respectively to get a displacement of the corresponding characteristic spot in each image and to further get a disparity map; and applying the displacement between the two corresponding characteristic spots in the corresponding images and synthesizing the images to form a synthetic image.

Abstract: The present invention discloses a fiber-optic localized plasmon resonance (FO-LPR) sensing device and a sensing system thereof, the FO-LPR sensing system includes a light source, a FO-LPR sensing device and a detector, and the light source provides a light beam entered into the FO-LPR sensing device, and the detector generates a detected signal according to an emergent light from the FO-LPR sensing device. The FO-LPR sensing device includes an optical fiber, a noble metal nanoparticle layer and a filter film layer. The filter film layer is having a porous material, and the porous material comes with a pore diameter or a property selected according to a feature of a sample, while an interfering substance in the sample is isolated.

Abstract: A method for high dynamic range imaging includes the steps of arranging at least two cameras parallel and meanwhile capturing a plurality of images of one scene with different exposures by the at least two cameras; adjusting the captured images for the same exposure thereof subject to the response functions of the cameras respectively and then defining a plurality of characteristic spots in each of the images; combining the characteristic spots corresponding to the images respectively to get a displacement of the corresponding characteristic spot in each image and to further get a disparity map; and applying the displacement between the two corresponding characteristic spots in the corresponding images and synthesizing the images to form a synthetic image.

Abstract: The present invention discloses a fiber-optic localized plasmon resonance (FO-LPR) sensing device and a sensing system thereof, the FO-LPR sensing system includes a light source, a FO-LPR sensing device and a detector, and the light source provides a light beam entered into the FO-LPR sensing device, and the detector generates a detected signal according to an emergent light from the FO-LPR sensing device. The FO-LPR sensing device includes an optical fiber, a noble metal nanoparticle layer and a filter film layer. The filter film layer is having a porous material, and the porous material comes with a pore diameter or a property selected according to a feature of a sample, while an interfering substance in the sample is isolated.

Abstract: A plasmon resonance sensing system includes a light source, a waveguide component and a photon detector. The light source provides an incident light. The waveguide component has a tubular internal wall and a noble metal nanoparticle layer disposed on the tubular internal wall and contacted with a desired testing matter. The waveguide component is made of a light transmitting material for guiding the incident light to have an interaction with the noble metal nanoparticle layer. The photon detector detects an emergent light exiting the waveguide component after the interaction of the noble metal nanoparticle layer with the desired testing matter. The system further includes a first optical fiber installed between the light source and the waveguide component for transmitting the incident light to the waveguide component, a lens and a second optical fiber. The lens collects and transmits the emergent light to the photon detector through the second optical fiber.

Abstract: The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory.

Abstract: A NAND type non-volatile memory having a plurality of bit lines and a dummy bit line is provided. The intersections of each of the bit lines with a first select gate line, a plurality of word lines, and a second select gate line are corresponding to a memory cell row. The intersections of the dummy bit line with the first select gate line, the word lines, and the second select gate line are corresponding to a dummy memory cell row. A source line is disposed on the substrate at one side of the memory cell rows, wherein the dummy memory cell row and the dummy bit line are served as a current path for connecting the source line.

Abstract: A non-volatile memory includes a substrate, a memory unit array, (N+1) bit lines, M word lines, M first control gate lines, and M second control gate lines. The memory unit array includes N memory unit columns, and each memory unit column includes M memory units. The (N+1) bit lines are disposed on the substrate and arranged in parallel in the column direction, and the (N+1) bit lines are corresponding to the N memory unit columns. The M word lines are disposed on the substrate and arranged in parallel in the row direction. The M first control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the first memory cell in the same row. The M second control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the second memory cell in the same row.

Abstract: A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

Abstract: A manufacturing method for a non-volatile memory includes first providing a substrate with a gate structure formed thereon. The gate structure includes a first gate and a gate dielectric layer located between the first gate and the substrate. A first doping and a second doping region are formed on the substrate at two sides of the gate, respectively. A first insulating layer is formed on the substrate, and a portion of the first insulating layer and a portion of the substrate are removed to form a trench, which divides the second doping region into a third doping region and a fourth doping region. Finally, a tunneling dielectric layer, a charge-trapping layer and a top dielectric layer are formed inside the trench, and a second gate which fills the trench is formed on the substrate.

Abstract: An operating method for a non-volatile memory device is applicable on a non-volatile memory device in which a substrate is disposed. The substrate includes a trench, a first conductive type first well region disposed in the substrate, and a second conductive type second well region disposed above the first conductive type first well region. The operating method includes applying a first voltage to a control gate, a second voltage to a drain region, and a third voltage to a source region. Besides, a channel F-N tunneling effect is employed to program a memory cell.

Abstract: The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory.

Abstract: A nonvolatile memory is provided. The memory includes a select transistor and a trench transistor. The select transistor is formed on the substrate. The select transistor includes a first gate formed on the substrate and first and second source/drain regions formed in the substrate next to the first gate. The trench transistor is formed in the substrate. The trench transistor includes a second gate formed in the trench of substrate, an electron trapping layer formed between the second gate and the trench and second and third source/drain regions formed in the substrate next to the second gate. The select transistor and the trench transistor share the second source/drain region.

Abstract: A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate. The p type well is formed in the substrate above the n type well. The junction of p type well and the n type well is higher than the bottom of the trench. The control gate which protruding the surface of substrate is formed on the sidewalls of the trench. The composite dielectric layer is formed between the control gate and the substrate. The composite dielectric layer includes a charge-trapping layer. The source region and the drain region are formed in the substrate of the bottom of the trench respectively next to the sides of the control gate.

Abstract: A one-time programmable read only memory is provided. The memory includes a substrate, a select transistor, an electrode and a dielectric layer. The select transistor is formed on the substrate. The electrode is formed over the source region of the select transistor. The dielectric layer is formed between the electrode and the source region of the select transistor. Digital data is stored in the memory through the breakdown or not of the dielectric layer.

Abstract: A method of manufacturing a well pick-up structure of a non-volatile memory is provided. A substrate including a first conductive type well, device isolation structures and dummy memory columns is provided. Each of the dummy memory columns includes a second conductive type source region and a second conductive type drain region. A first interlayer insulating layer with an opening is formed over the substrate, and the opening exposes the two adjacent second conductive type drain regions and the device isolation structure between the two adjacent second conductive type drain regions. A portion of the device isolation structure exposed by the opening is removed, and then a first conductive type well extension doped region is formed in the substrate exposed by the opening. A well pick-up conductive layer is formed in the opening. Dummy bit lines electrically connecting the well pick-up conductive layer are formed over the substrate.

Abstract: A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.

Abstract: A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.