Abstract: An imaging lens includes a lens element, a lens barrel, an arm, a holder and a retainer. The lens element has an optical axis. The lens barrel accommodates the lens element. The arm is disposed on the lens barrel and extends along a direction away from the optical axis. The holder has a first contacting surface in contact with the arm in a direction parallel to the optical axis. The retainer is fixed on the holder and has a second contacting surface in contact with the arm in a direction parallel to the optical axis. The first contacting surface and the second contacting surface are located on opposite sides. The arm is disposed between the holder and the retainer. The first contacting surface and the second contacting surface surround the optical axis and are non-overlapped with each other in a direction parallel to the optical axis.

Abstract: A clock synthesizer is provided. A clock buffer is configured to store an input clock signal. A Duty Cycle Corrector (DCC) circuit is connected to the clock buffer. The DCC circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. An output clock signal comprising the duty cycle corrected input clock signal is generated. The output clock signal is provided. A current source is configured to sink a clamping current to the DCC circuit.

Abstract: A system (for determining a lineup amongst a roster of all PFETs and all NFETs that are slaves in a subject group of pull-up-pull-down-inverters (PUDIs) that are coupled in parallel) includes: a comparator to make a comparison between a reference voltage and an output of the subject group. The controller performs: an assessment of a candidate lineup chosen from the roster including setting states of PFET-selection selection signals and NFET-selection signals according to the candidate lineup, and a manipulation based on the comparison including setting the starting-lineup to be the candidate lineup or modifying the candidate lineup and repeating the assessment and manipulation.

Abstract: A system includes a plurality of semiconductor chips that are stacked on top of each other and that include first and second semiconductor chips. The first semiconductor chip includes a clock signal generating circuit, a transmitting circuit, and a receiving circuit. The clock signal generating circuit generates a clock signal and a delayed version of the clock signal. The transmitting circuit transmits a first data signal in response to the clock signal. The receiving circuit receives a second data signal in response to the delayed version of the clock signal. For example, the receiving circuit receives the delayed version of the clock signal at substantially the same time that the transmitting circuit receives the clock signal.

Abstract: A method of manufacturing a semiconductor device based on a dual-architecture-compatible design includes: forming transistor components of in a transistor (TR) layer; and performing one of fabricating additional components according to (A) a buried power rail (BPR) type of architecture or (B) a non-buried power rail (non-BPR) type of architecture. The step (A) includes, in corresponding sub-TR layers, forming various non-dummy sub-TR structures, and, in corresponding supra-TR layers, forming various dummy supra-TR structures which are corresponding first artifacts. The step (B) includes, in corresponding supra-TR layers, forming various non-dummy supra-TR structures and forming various dummy supra-TR structures which are corresponding second artifacts, the first and second artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR type of architecture.

Abstract: Circuits, devices, and methods relating to a phase interpolator are described herein. The phase interpolator may comprise a first plurality of functional units and a second plurality of functional units, and may be controlled, in part, by an encoding scheme. The phase interpolator may be designed to have a layout such that a turn-on resistance across the first plurality of functional units in response to a first code of the encoding scheme is equal to a turn-on resistance across the second plurality of functional units in response to a second code of the encoding scheme.

Abstract: A package structure includes a first die and a second die adjacent to the first die. A redistribution structure is above and electrically connected with the first and second die. The redistribution structure includes a first conductive line electrically connecting the first die to the second die, and a first conductive via in contact with the first conductive line and overlapping a die-to-die region between the first and second dies. A third die is over and electrically connected with the redistribution structure. An external connector is over electrically connected with the third die.

Abstract: An embodiment of an integrated circuit may comprise a circuit block and a power management circuit coupled to the circuit block to manage two or more power states for the circuit block and to manage a request for the circuit block to enter a requested power state of the two or more power states, set a watchdog timer in response to the request, and monitor the watchdog timer and a transition of the circuit block from a current power state to the requested power state. Other embodiments are disclosed and claimed.

Abstract: A control circuit is coupled to a power converter having an input voltage VIN and an output voltage VOUT. The control circuit includes a capacitor connected between a current source and a ground. The current source is configured to charge the capacitor with a current ?VIN or ?(VIN?VOUT) when a pulse width modulate (PWM) signal of a PWM controller of the power converter is high, and to discharge the capacitor with a current ?(?VOUT) or ?(VIN?VOUT) when the PWM signal is low. ? is a pre-configured constant. The control circuit is configured to trigger the PWM controller to skip pulses when a voltage across the capacitor decreases to be less than a threshold before a present switching cycle of the power converter ends.

Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

Abstract: The present disclosure provides a receiver circuit, which includes: a first comparator circuit, a second comparator circuit, and an inverter circuit. The inverter circuit has a first input terminal and a second input terminal. A first output terminal of the first comparator circuit is electrically connected to the first input terminal of the inverter circuit, and a second output terminal of the second comparator circuit is electrically connected to the second input terminal of the inverter circuit.

Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

Abstract: An overhead transport vehicle is described for association with an Automated Material Handling System (AMHS). The overhead transport vehicle provides features to the AMHS by which the AMHS is able to reduce a number of manual urgent lot rescues by the fab operator when a logistic algorithm controlling traffic in the AMHS is unable to transport the front opening unified pods (FOUP) from one tool to the subsequent tool in the sequence of the process steps within the q-time due to unexpected problems. An indicator on the overhead transport vehicle which helps the fab operator with spotting a lot in trouble is described. A backup power source on the overhead transport vehicle used in case of a main power failure is also described.

Abstract: An overhead transport vehicle is described for association with an Automated Material Handling System (AMHS). The overhead transport vehicle provides features to the AMHS by which the AMHS is able to reduce a number of manual urgent lot rescues by the fab operator when a logistic algorithm controlling traffic in the AMHS is unable to transport the front opening unified pods (FOUP) from one tool to the subsequent tool in the sequence of the process steps within the q-time due to unexpected problems. An indicator on the overhead transport vehicle which helps the fab operator with spotting a lot in trouble is described. A backup power source on the overhead transport vehicle used in case of a main power failure is also described.

Abstract: A method, system, and article provide image processing with power reduction while using universal serial bus cameras.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.

Abstract: A clock synthesizer is provided. A clock buffer is configured to store an input clock signal. A Duty Cycle Corrector (DCC) circuit is connected to the clock buffer. The DCC circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. An output clock signal comprising the duty cycle corrected input clock signal is generated. The output clock signal is provided. A current source is configured to sink a clamping current to the DCC circuit.

Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.

Abstract: A semiconductor package according to the present disclosure includes a routing structure, a first die and a second die disposed over the routing structure, a first array of contact features disposed along a first direction and electrically coupling the first die to the routing structure, and a second array of contact features disposed along the first direction and electrically coupling the second die to the routing structure. The routing structure includes a plurality of metal lines and each of the plurality of metal lines electrically connects one of the first array of contact features and one of the second array of contact features. Each of the plurality of metal lines comprises at least two 90-degree turns on a horizontal plane.