Patents by Inventor Weilun Hong
Weilun Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10971370Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: GrantFiled: December 16, 2019Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20210020449Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.Type: ApplicationFiled: July 18, 2019Publication date: January 21, 2021Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
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Publication number: 20200365413Abstract: A method includes forming a film over a substrate; increasing a surface roughness of the film; and planarizing the film using a first chemical mechanical planarization (CMP) process after increasing the surface roughness.Type: ApplicationFiled: May 17, 2019Publication date: November 19, 2020Inventors: Po-Chin Nien, Gang Huang, William Weilun Hong
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Publication number: 20200279751Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.Type: ApplicationFiled: May 19, 2020Publication date: September 3, 2020Inventors: Chun-Wei Hsu, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Yang-Chun Cheng
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Patent number: 10692732Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.Type: GrantFiled: September 21, 2018Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Wei Hsu, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, William Weilun Hong, Chi-hsiang Shen, Chia-Wei Ho, Yang-chun Cheng
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Publication number: 20200126803Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: Wan-Chun Pan, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20200118827Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20200105668Abstract: A semiconductor device includes a first dielectric layer over a substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer distal from the substrate to a second side of the first dielectric layer opposing the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line including a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap being over and physically connected to the conductive line, the metal cap including a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via including the second conductive material.Type: ApplicationFiled: July 29, 2019Publication date: April 2, 2020Inventors: Chia-Wei Ho, Chun-Wei Hsu, Chi-Hsiang Shen, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
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Publication number: 20200098591Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.Type: ApplicationFiled: May 1, 2019Publication date: March 26, 2020Inventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng
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Publication number: 20200098590Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.Type: ApplicationFiled: September 21, 2018Publication date: March 26, 2020Inventors: Chun-Wei Hsu, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, William Weilun Hong, Chi-hsiang Shen, Chia-Wei Ho, Yang-chun Cheng
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Patent number: 10541139Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.Type: GrantFiled: March 24, 2016Date of Patent: January 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Patent number: 10522365Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.Type: GrantFiled: June 14, 2016Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan-Chun Pan, William Weilun Hong, Ying-Tsung Chen
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Patent number: 10510552Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: GrantFiled: April 20, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manfacturing Company, Ltd.Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Patent number: 10068988Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.Type: GrantFiled: January 2, 2018Date of Patent: September 4, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
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Publication number: 20180240679Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: April 20, 2018Publication date: August 23, 2018Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20180145152Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.Type: ApplicationFiled: January 2, 2018Publication date: May 24, 2018Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
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Patent number: 9960050Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: GrantFiled: August 5, 2013Date of Patent: May 1, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9941109Abstract: A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high pressure rinse on the wafer while the wafer is positioned on the platen, wherein the high pressure rinse includes a hydrophilic solution. The wafer is soaked in the hydrophilic solution, and after soaking the wafer, the wafer is cleaned.Type: GrantFiled: June 29, 2016Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9922837Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.Type: GrantFiled: March 2, 2016Date of Patent: March 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9871115Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.Type: GrantFiled: July 1, 2016Date of Patent: January 16, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen