Patents by Inventor Weilun Hong
Weilun Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180005840Abstract: A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high pressure rinse on the wafer while the wafer is positioned on the platen, wherein the high pressure rinse includes a hydrophilic solution. The wafer is soaked in the hydrophilic solution, and after soaking the wafer, the wafer is cleaned.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20180006134Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.Type: ApplicationFiled: July 1, 2016Publication date: January 4, 2018Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
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Publication number: 20170278712Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.Type: ApplicationFiled: March 24, 2016Publication date: September 28, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20170256414Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.Type: ApplicationFiled: March 2, 2016Publication date: September 7, 2017Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9721831Abstract: A method includes forming a plurality of first semiconductor fins and a plurality of second semiconductor fins in a substrate, depositing a gate electrode layer over the substrate, wherein upper portions of the plurality of first semiconductor fins and the plurality of second semiconductor fins are embedded in the gate electrode layer, depositing a reverse film over the gate electrode layer and applying a chemical mechanical polish process to the reverse film and the gate electrode layer, wherein during the step of applying the chemical mechanical polish process, depositing a slurry between a polishing pad and the reverse film, and wherein a slurry selectivity ratio of the gate electrode layer to the reverse film is greater than 1.Type: GrantFiled: December 3, 2015Date of Patent: August 1, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20170213743Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.Type: ApplicationFiled: June 14, 2016Publication date: July 27, 2017Inventors: Wan-Chun Pan, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9711374Abstract: Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation.Type: GrantFiled: June 13, 2013Date of Patent: July 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Che-Hao Tu, Chih-Yu Chang, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20170162432Abstract: A method includes forming a plurality of first semiconductor fins and a plurality of second semiconductor fins in a substrate, depositing a gate electrode layer over the substrate, wherein upper portions of the plurality of first semiconductor fins and the plurality of second semiconductor fins are embedded in the gate electrode layer, depositing a reverse film over the gate electrode layer and applying a chemical mechanical polish process to the reverse film and the gate electrode layer, wherein during the step of applying the chemical mechanical polish process, depositing a slurry between a polishing pad and the reverse film, and wherein a slurry selectivity ratio of the gate electrode layer to the reverse film is greater than 1.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Inventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9595450Abstract: A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.Type: GrantFiled: December 26, 2013Date of Patent: March 14, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9278423Abstract: A method for breaking up Chemical Mechanical Polishing (CMP) slurry particles includes receiving a CMP slurry comprising particles suspended in a solution, placing the slurry into a first agitation tank, and agitating the slurry at a first frequency. The first frequency is selected to break up particles having a size within a specified range.Type: GrantFiled: October 8, 2013Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: William Weilun Hong, Kuo-Min Lin, Ying-Tsung Chen
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Publication number: 20150187594Abstract: A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20150099431Abstract: A method for breaking up Chemical Mechanical Polishing (CMP) slurry particles includes receiving a CMP slurry comprising particles suspended in a solution, placing the slurry into a first agitation tank, and agitating the slurry at a first frequency. The first frequency is selected to break up particles having a size within a specified range.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: William Weilun Hong, Kuo-Min Lin, Ying-Tsung Chen
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Patent number: 8975179Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.Type: GrantFiled: October 18, 2011Date of Patent: March 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Hao Tu, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen
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Publication number: 20150037978Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: August 5, 2013Publication date: February 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHE-HAO TU, WILLIAM WEILUN HONG, YING-TSUNG CHEN
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Publication number: 20140370696Abstract: Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation.Type: ApplicationFiled: June 13, 2013Publication date: December 18, 2014Inventors: Che-Hao TU, Chih-Yu CHANG, William Weilun HONG, Ying-Tsung CHEN
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Patent number: 8598028Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.Type: GrantFiled: December 22, 2011Date of Patent: December 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Hao Tu, Chi-Jen Liu, Tzu-Chung Wang, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen
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Publication number: 20130164930Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Che-Hao Tu, Chi-Jen Liu, Tzu-Chung Wang, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen
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Publication number: 20130095644Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Che-Hao Tu, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen