Abstract: A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 ?m to 10 ?m.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

Abstract: The available delivery capability (ADC) of a power distribution network with respect to a power transaction is evaluated in real-time. The power transaction involves simultaneous power deliveries from power sources in a source area to loads in a sink area. First, a list of contingencies are ranked in the power distribution network with respect to static security constraints to obtain a subset of top-ranked contingencies. For each top-ranked contingency in the subset, a representation of the power transaction in a steady state of the power distribution network, in a form of parameterized three-phase power flow equations, is solved to obtain a corresponding power delivery capability (PDC) and a corresponding binding constraint among the static security constraints. The reliability of the power transaction in the power distribution network is then evaluated based on, at least in part, a first contingency PDC which is a smallest PDC among obtained corresponding PDCs.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.

Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.

Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.

Abstract: A method of forming a semiconductor structure is disclosed. A fin structure is formed on a substrate and a trench is formed in the fin structure. The trench has a top corner, an upper portion having an upper sidewall and a lower portion having a lower sidewall. A first dielectric layer is then formed on the substrate and fills the lower portion of the trench. After that, a second dielectric layer is formed on the substrate and covers the top corner and the upper sidewall of the trench. The second dielectric layer also covers an upper surface of the first dielectric layer.

Abstract: An inhibitor of a wild type and Y641F mutant of human histone methyltransferase EZH2 is provided herein. Particularly, the inhibitor is a compound represented by formula (I) or a pharmaceutically acceptable salt thereof. The inhibitor can be used to treat a cancer or precancerous condition related to EZH2 activity.

Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.

Abstract: The disclosure relates to a board-to-board connector including a body, multiple terminals and a pair of metal fittings. The body has an accommodating recess. The terminal is disposed on the body and a portion of each of the terminals extends to the accommodating recess. The metal fittings are disposed on the body and beside the accommodating recess. The terminals are located between metal fittings. Each of the metal fittings has at least one limiting portion that extends to the accommodating recess. The limiting portion leans against a corner of the accommodating recess so that the metal fittings and the body generate a two-dimensional limitation. A board-to-board connector assembly is also provided.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.

Abstract: A narrower LED package structure with sideways output of light suitable for a light guide plate includes two first electrodes, a package body, a cover layer, and two second electrodes. The LED chip is mounted on the first electrodes. The package body encapsulates the first electrodes, and surrounds the LED chip to define a light emitting region. The cover layer infills the light emitting region and covers the LED chip. The second electrodes are positioned outside the package body. Along a plane parallel to the first electrodes, a surface area of the two second electrodes is greater than a surface area of the portion of the two first electrodes positioned in the light emitting region.

Abstract: An embedded component structure including a circuit board, an electronic component, a dielectric layer and a connection circuit layer and a manufacturing method thereof is provided. The circuit board has a through hole and includes a core layer, a first circuit layer, and a second circuit layer. The first circuit layer and the second circuit layer are disposed on the core layer. The through hole penetrates the first circuit layer and the core layer. The electronic component including a plurality of connection pads is disposed within the through hole where the dielectric layer is filled in. The Young's modulus of the core layer is greater than the Young's modulus of the dielectric layer. The connection circuit layer covers and contacts a first electrical connection surface of the first circuit layer and at least one of a second electrical connection surface of each of the connection pads. A manufacturing method of an embedded component structure is also provided.

Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.

Abstract: A multiple rhombic dodecahedron puzzle includes a plurality of wooden puzzles arranged in a multiple rhombic dodecahedron. The multiple rhombic dodecahedron is equivalent to a cube formed by a plurality of rhombic dodecahedrons connecting to each other. Each of the wooden puzzles includes two unit elements. The two unit elements are connected to each other and are the same others. Each of the two unit elements has a plurality of surfaces. Each of the surfaces has a diamond shape or a triangular shape. Two of the surfaces which in the triangular shape are connected to each other in order to form a concave shape, and the surfaces are surrounded to form a closed space.

Abstract: An inhibitor of a wild type and Y641 F mutant of human histone methyltransferase EZH2 is provided herein. Particularly, the inhibitor is a compound represented by formula (I) or a pharmaceutically acceptable salt thereof. The inhibitor can be used to treat a cancer or precancerous condition related to EZH2 activity.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to forma first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.

Abstract: A package structure includes a substrate, a metal-insulator-metal capacitor, a circuit redistribution structure, and a chip. The metal-insulator-metal capacitor is disposed over the substrate and includes a first electrode, a second electrode, and an insulating layer. The circuit redistribution structure is disposed over the metal-insulator-metal capacitor and includes a first circuit redistribution layer and a second circuit redistribution layer. The first circuit redistribution layer includes a first wire electrically connected to the first electrode and a second wire electrically connected to the second electrode. The second circuit redistribution layer is disposed on the first circuit redistribution layer and includes a third wire electrically connected to the first wire and a fourth wire electrically connected to the second wire. The chip is disposed over the circuit redistribution structure and electrically connected to the third wire and the fourth wire.