Abstract: A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a select gate, a control gate, an erase gate, and a floating gate. The select gate is disposed on the substrate. The control gate is disposed on the substrate and laterally spaced apart from the select gate. The erase gate is disposed on the substrate and laterally spaced apart from the control gate, and the erase gate includes a concave corner. The floating gate is covered with the control gate and the erase gate. The floating gate includes a convex corner which faces the concave corner of the erase gate, and the vertex of the floating gate is lower than a top surface of the select gate.

Abstract: A method of screening new psychoactive substance is provided, including providing a sample; placing the sample on chromatographic paper; ionizing the sample on the chromatographic paper by a direct analysis in real time (DART); performing a mass spectrometry analysis on the ionized sample to obtain a sample mass spectrum; and comparing a known standard mass spectrum with the sample mass spectrum, in which when a profile of the known standard mass spectrum is the same as a profile of the sample mass spectrum and the known standard mass spectrum is not exactly the same as the sample mass spectrum, the sample is determined to be the new psychoactive substance. A platform for screening new psychoactive substance is also provided to quickly screen out the new psychoactive substance.

Abstract: In some embodiments, the present disclosure relates to an integrated device, including a substrate; a gate overlying the substrate; a channel layer separated from the gate by a dielectric and overlying the gate; source/drain regions on the channel layer, the gate extending between the source/drain regions; an insertion layer conforming to an upper surface of the channel layer and comprising a first material; and a passivation layer conforming to an upper surface of the insertion layer and comprising a second material different from the first material; where the passivation layer has a higher density than the insertion layer, such that the passivation layer mitigates the diffusion of environmental materials towards the channel layer, and where the insertion layer mitigates the diffusion of the second material from the passivation layer into the channel layer.

Abstract: A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a trench, an erase gate, a control gate, and a floating gate. The trench is disposed in the substrate. The erase gate is disposed in the trench and includes a concave corner. The control gate is disposed on the substrate, and a bottom surface of the control gate is higher than a bottom surface of the erase gate. The floating gate is disposed on the substrate, and the floating gate includes a lower tip pointing toward the concave corner of the erase gate and extending beyond a sidewall of the trench.

Abstract: The present disclosure provides a method for executing random access resource selection in UE served by an NTN. The method includes: detecting a synchronization signal block (SSB) transmitted by an NTN cell, based on a predefined communication resource associated with the SSB; determining an identifier (ID) associated with the detected SSB; maintaining assistance information, wherein the assistance information comprises at least one of the following: first information associated with a presentation order of the detected SSB; and second information associated with an available service duration d of a random access resource associated with the detected SSB; selecting one of the detected SSB as a first SSB based on the assistance information when a plurality of SSB are detected; and applying a random access resource associated with the first SSB for performing a random access procedure.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and a membrane adjacent to the substrate and configured to generate charges in response to an acoustic wave. The membrane includes a via pattern including: first lines that partition the membrane into slices and extend to a side of the membrane such that the slices are separated from each other near the side of the membrane and connected to each other around a central region, wherein the first lines are made closer to each other when they are closer to the central region, and second lines alternatingly arranged with the first lines.

Abstract: In some embodiments, the present disclosure relates to an integrated device, including: a substrate; a semiconductor layer on the substrate and including a first structure being one of a sound port, a sealed cavity, or a proof mass, and a second structure being one of the sound port, the sealed cavity, or the proof mass, where the second structure is a different one of the sound port, the sealed cavity, or the proof mass than the first structure; a piezoelectric layer on the semiconductor layer overlying the first structure and the second structure; and an air gap extending into the semiconductor layer from an upper surface of the piezoelectric layer, wherein the first structure and portions of the piezoelectric layer overlying the first structure are spaced from the second structure and portions of the piezoelectric layer overlying the second structure by the air gap.

Abstract: An abnormal detection circuit is provided. The abnormal detection circuit includes a conversion circuit, a voltage detection circuit, and a warning circuit. The conversion circuit receives a three-phase alternating current (AC) power and converts the three-phase AC power into a driving power. The voltage detection circuit detects each phase of the three-phase AC power. When a voltage value of at least one phase AC power of the three-phase AC power is abnormal, the voltage detection circuit uses the driving power to output at least one control signal corresponding to the abnormality. The warning circuit is driven by receiving the driving power and outputs at least one warning signal corresponding to the abnormality in response to the at least one control signal.

Abstract: A system and method for chemical mechanical polishing (“CMP”) pad replacement on a CMP processing tool. A platen carrier having two or more platens is positioned within a platen cleaning process module. Each platen includes a CMP pad affixed thereto, and is capable of being independently rotated during operations. When a pad requires replacement, the platen carrier rotates towards a pad tearer tool, which extends and pivots to remove the used pad from the platen as the carrier rotates. A pad tape replacement module is positioned above the CMP tool with pad tape extending from a supply roll to a recycle roll. As the pad tape transits through the module, a backing of the tape is separated and recycled. A pad disposed in the pad tape is then applied to a platen via a pressure roller.

Abstract: A method for preparing a polyester modified material from a recycled release film includes continuously performing the following steps at an elevated temperature: subjecting the recycled release film to a first melting treatment to form a low-viscosity polyester; subjecting the low-viscosity polyester to a polymerization treatment to form a high-viscosity polyester, wherein a viscosity of the high-viscosity polyester is greater than a viscosity of the low-viscosity polyester; and adding a modifier to the high-viscosity polyester to perform a second melting treatment to form the polyester modified material.

Abstract: A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

Abstract: Disclosed are a magnetic core structure and a magnetic component. The magnetic core structure includes N winding columns and two cover plates, and N is a positive integer, wherein each winding column is provided with a first hollow channel, the two cover plates are disposed at two ends of each winding column, each cover plate is provided with N first through holes, the N winding columns are in a one-to-one correspondence with the N first through holes of each cover plate, and the first hollow channel of each winding column is communicated with the first through holes located on two sides thereof and corresponding thereto. Therefore, the channels for air flow can be added, so that the heat dissipation efficiency is improved when the magnetic core structure is applied to the magnetic component.

Abstract: The invention introduces an apparatus and a method for expanding round keys during data encryption. The method includes: configuring a word-processing circuitry to operate in a first mode to calculate a first intermediate calculation result corresponding to an even-number round key according to a last double word of a 0th double word to a 7th double word in each even-number clock cycle starting from a 2nd clock cycle; and configuring the word-processing circuitry to operate in a second mode to calculate a second intermediate calculation result corresponding to an odd-number round key according to the last double word of the 0th double word to the 7th double word in each odd-number clock cycle starting from a 3rd clock cycle. In the first mode, a first data path is formed in the word-processing circuitry, which includes a word split circuitry, a rotate-word circuitry, a substitute-word circuitry, a round-constant circuitry and a word concatenation circuitry.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: Disclosed is a vacuum chuck and a method for securing a warped semiconductor substrate during a semiconductor manufacturing process so as to improve its flatness during a semiconductor manufacturing process. For example, a semiconductor manufacturing system includes: a vacuum chuck configured to hold a substrate, wherein the vacuum chuck comprises, a plurality of vacuum grooves located on a top surface of the vacuum chuck, wherein the top surface is configured to face the substrate; and a plurality of flexible seal rings disposed on the vacuum chuck and extending outwardly from the top surface, wherein the plurality of flexible seal rings are configured to directly contact a bottom surface of the substrate and in adjacent to the plurality of vacuum grooves so as to form a vacuum seal between the substrate and the vacuum chuck, and wherein each of the plurality of flexible seal rings has a zigzag cross section.

Abstract: A light-emitting device array includes a first light-emitting device, a second light-emitting device, and a third light-emitting device. A first beam shaping structure of the first light-emitting device is configured to convert light emitted by a first light-emitting structure of first light-emitting device into first structured light. A second beam shaping structure of the second light-emitting device is configured to convert light emitted by a second light-emitting structure of second light-emitting device into second structured light. Speckle patterns and spatial distributions of the first structured light and the second structured light on a projection plane are the same. A third beam shaping structure of the third light-emitting device is configured to convert light emitted by a third light-emitting structure of third light-emitting device into third structured light.

Abstract: The present invention provides a federated large model adaptive learning system. Based on the combination of multiobjective optimization and incremental learning, multiple optimization indexes are constructed, and adaptive mini model incremental learning is designed. A gradient scaling method of mini models is proposed for data privacy protection under federated learning, to make full use of gradient information. A correlation between the generalization ability and sampling data is revealed to propose a generalization ability evaluation function. With respect to the real problems of performance degradation and fault faced by industrial equipment during operation, multiple optimization objectives are designed in combination with the generalization ability evaluation function, and the models are updated and repaired adaptively through multiobjective evolutionary learning, to improve the usability of large models in real industrial scenarios.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.

Abstract: A micro-LED display includes a first LED subpixel, a second LED subpixel, a third LED subpixel and a fourth LED subpixel. The first LED subpixel is configured to emit a red light. The second LED subpixel is configured to emit a green light. The third LED subpixel is configured to emit a blue light. The fourth LED subpixel is configured to emit a yellow light, in which the yellow light emitted by the fourth LED subpixel has a peak wavelength that satisfies ?p,Yellow,lower_limit<?p. ?p,Yellow,lower_limit is a lower limit of the peak wavelength of the yellow light, ?p is the peak wavelength of the yellow light.

Abstract: An alloy material of polycarbonate-polyethylene terephthalate includes the following components: a polycarbonate, a polyethylene terephthalate, a transesterification inhibitor, and a compatibilizer.