Abstract: A coolant distribution device includes a housing, a heat exchanger, a first inlet port, a first outlet port, at least one pump assembly, and a first power connector. The housing has at least one opening. The heat exchanger and the at least one pump assembly are disposed in the housing. The first inlet port and the first outlet port are connected to the heat exchanger. A part of the at least one pump assembly passes through the at least one opening and is exposed from the housing. The at least one pump assembly is interconnected with the first inlet port and the heat exchanger. The first power connector is disposed on the housing and is configured to receive DC power.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A projection device includes a light source module, a display panel, a freeform-surface reflective mirror, and a projection lens. The light source module includes a light source, a first Fresnel lens element, and a second Fresnel lens element. The first Fresnel lens element and the second Fresnel lens element are parallel to each other and located between the light source and the display panel. The display panel is arranged between the light source module and the freeform-surface reflective mirror. The projection lens is configured to transmit an image beam out of the projection device, and a direction of an optical axis of the projection lens is different from a direction of a normal of the first Fresnel lens element.

Abstract: An electronic device includes a first metal layer, a first insulating layer disposed on the first metal layer, a second metal layer, a second insulating layer, a third metal layer, a third insulating layer, a fourth metal layer, a fourth insulating layer and an electronic component. The second metal layer is disposed on the first insulating layer. The second insulating layer is disposed on the second metal layer. The third metal layer is disposed on the second insulating layer. The third insulating layer is disposed on the third metal layer. The fourth metal layer is disposed on the third insulating layer. The fourth insulating layer is disposed on the fourth metal layer. The electronic component is disposed on the fourth insulating layer and electrically connected to the fourth metal layer. A Young's modulus of the third insulating layer is less than a Young's modulus of the first insulating layer.

Abstract: An electronic component includes a first electronic unit including a plurality of pads, a first conductive layer, a second conductive layer, a first insulating layer having a first thickness, a second insulating layer having a second thickness, a second electronic unit, and a solder ball. The first conductive layer is disposed between the first electronic unit and the second conductive layer, and electrically connected to at least one of the pads through a conductive via. The first insulating layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer is disposed between the first insulating layer and the second insulating layer. The first thickness is different from the second thickness. The second conductive layer is disposed between the first conductive layer and the second electronic unit. The second conductive layer is electrically connected to the second electronic unit through the solder ball.

Abstract: The present application discloses an amplifier circuit, a chip and an electronic device, which generates a positive output signal and a negative output signal according to a positive input signal and a negative input signal, wherein the positive input signal and the negative input signal have a corresponding input differential-mode voltage and input common-mode voltage, and the positive output signal and the negative output signal have a corresponding output differential-mode voltage and output common-mode voltage, and the amplifier circuit includes: an amplifying unit, configured to receive the positive input signal and the negative input signal and generate the positive output signal and the negative output signal; and an attenuation unit, including: a positive common-mode capacitor and a negative common-mode capacitor, configured to attenuate the input common-mode voltage below a first specific frequency.

Abstract: The present application discloses a transconductance amplifier and a related chip. The transconductance amplifier is configured to generate an output current according to a positive input voltage and a negative input voltage, wherein the transconductance amplifier includes: an input stage, configured to receive the positive input voltage and the negative input voltage and generate a positive output current and a negative output current, wherein the input stage includes: a first transistor, wherein a gate thereof is coupled to the positive input voltage; a second transistor, wherein a gate thereof is coupled to the negative input voltage; a first resistor, serially connected between the first transistor and the second transistor; a third transistor, wherein a source of the third transistor is coupled between the first resistor and the first transistor, and a drain of the third transistor is configured to output the positive output current; and a fourth transistor.

Abstract: The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

Abstract: The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

Abstract: The present application discloses a voltage booster circuit and a related circuit, chip and wearable device. The voltage booster circuit has an output terminal, which provides an output voltage and a load current. The voltage booster circuit includes: a first charge pump, which provides a first bias current; a second charge pump, which provides the load current; an output voltage fixing circuit, which draws the first bias current from the first charge pump to the output terminal, wherein the output voltage fixing circuit fixes a first charge pump voltage of the first charge pump by fixing the first bias current and further fixes the output voltage based on the fixed first charge pump voltage; and a load current generation circuit, which draws the load current from the second charge pump to the output terminal based on a second charge pump voltage of the second charge pump.

Abstract: The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

Abstract: The present application discloses an ADC (10). The ADC has an A/D conversion operation mode and a measurement operation mode. The ADC includes an input terminal (100), a DAC (104), and an output terminal (102). The input terminal is configured to receive an analog signal. The output terminal is configured to output a digital signal. The DAC includes a plurality of D/A conversion units. When the ADC operates in the A/D conversion operation mode, the ADC is configured to convert the analog signal into the digital signal, and when the ADC operates in the measurement operation mode, the digital signal related to a ratio of a capacitance of the D/A conversion unit to be measured to a total capacitance of the plurality of D/A conversion units.

Abstract: The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

Abstract: The present application discloses a PPG circuit, a biological characteristics detection device and a biological characteristics detection method. The PPG circuit is configured to control a light source and N photoelectric converters to sense biological characteristics of an object under test; the PPG circuit includes: a transmitting channel, K receiving channels, wherein the N photoelectric converters are divided into K sets of photoelectric converter sets, and the K receiving channels respectively correspond to K sets of photoelectric converter sets; and a controller, configured to control the PPG circuit to operate in a partial sampling phase or an full sampling phase, so as to generates J or K biological characteristics sampling results during each of the pulse repetition cycles.

Abstract: The present application discloses a voltage booster circuit and a related circuit, chip and wearable device. The voltage booster circuit has an output terminal, which provides an output voltage and a load current. The voltage booster circuit includes: a first charge pump, which provides a first bias current; a second charge pump, which provides the load current; an output voltage fixing circuit, which draws the first bias current from the first charge pump to the output terminal, wherein the output voltage fixing circuit fixes a first charge pump voltage of the first charge pump by fixing the first bias current and further fixes the output voltage based on the fixed first charge pump voltage; and a load current generation circuit, which draws the load current from the second charge pump to the output terminal based on a second charge pump voltage of the second charge pump.

Abstract: The present application discloses a transconductance amplifier and a related chip.

Abstract: The present application discloses an amplifier circuit, a chip and an electronic device, which generates a positive output signal and a negative output signal according to a positive input signal and a negative input signal, wherein the positive input signal and the negative input signal have a corresponding input differential-mode voltage and input common-mode voltage, and the positive output signal and the negative output signal have a corresponding output differential-mode voltage and output common-mode voltage, and the amplifier circuit includes: an amplifying unit, configured to receive the positive input signal and the negative input signal and generate the positive output signal and the negative output signal; and an attenuation unit, including: a positive common-mode capacitor and a negative common-mode capacitor, configured to attenuate the input common-mode voltage below a first specific frequency.

Abstract: The present application discloses an ADC (10). The ADC has an A/D conversion operation mode and a measurement operation mode. The ADC includes an input terminal (100), a DAC (104), and an output terminal (102). The input terminal is configured to receive an analog signal. The output terminal is configured to output a digital signal. The DAC includes a plurality of D/A conversion units. When the ADC operates in the A/D conversion operation mode, the ADC is configured to convert the analog signal into the digital signal, and when the ADC operates in the measurement operation mode, the digital signal related to a ratio of a capacitance of the D/A conversion unit to be measured to a total capacitance of the plurality of D/A conversion units.

Abstract: An operational amplifier includes: a first amplifier stage, configured to generate first output voltages according to first input voltages; a second amplifier stage, configured to generate second output voltages according to the first output voltages; a second output stage circuit, configured to replicate an equivalent or a scaled-down version of the first output stage circuit; a first common-mode feedback circuit, configured to keep an output common-mode voltage of the second output stage circuit at a predetermined value; a logic loop circuit configured to, when the operational amplifier operates in a direct current calibration phase, adjust a difference between the first output voltages; a bias circuit, configured to generate a voltage close to a common-mode voltage of the first output voltages produced after the operational amplifier is turned on, the voltage serving as a reference voltage of a second common-mode feedback circuit.

Abstract: The application provides a charge pump circuit, includes a digital control circuit, coupled to the switch module, configured to receive a up digital signal and a down digital signal, and adjust a first output voltage to a voltage level of an input voltage and adjust an second output voltage to a ground voltage level according to the up digital signal and the down digital signal; a digital-to-analog converter (DAC), configured to generate a corresponding up reference voltage and a corresponding down reference voltage according to the up digital signal and the down digital signal; and a voltage follower, comprising a plurality of operational amplifiers and a plurality of transistor switches, configured to lock the first output voltage and the second output voltage according to the up reference voltage and the down reference voltage; wherein the up digital signal and the down digital signal are varied with time.