Abstract: An electronic component and a manufacturing method thereof are provided. The electronic component includes a structure member and a connecting member. The structure member includes at least one working unit. The at least one working unit is disposed in a first region. The connecting member is disposed on the structure member and includes a second region. The second region is overlapped with the first region, and a metal density of the second region is less than a metal density of the first region. The electronic component and the manufacturing method thereof of the embodiment of the disclosure include the effect of improving the reliability or quality of the electronic component.

Abstract: A manufacturing method of a package structure including the following steps is provided. A carrier is provided. An anti-warpage structure is formed on the carrier. And a redistribution layer is formed on the carrier. In the normal direction of the carrier, a warpage trend of the anti-warpage structure is opposite to a warpage trend of the redistribution layer.

Abstract: The present disclosure generally provides an apparatus and method for gas diffuser support structure for a vacuum chamber. The gas diffuser support structure comprises a backing plate having a central bore, and a gas deflector having a length and a width unequal to the length coupled to the backing plate by a plurality of outward fasteners coupled to a plurality of outward threaded holes formed in the backing plate, in which a spacer is disposed between the backing plate and the gas deflector, and in which a length to width ratio of the gas deflector is about 0.1:1 to about 10:1.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: The present application discloses an amplifier circuit, a chip and an electronic device, which generates a positive output signal and a negative output signal according to a positive input signal and a negative input signal, wherein the positive input signal and the negative input signal have a corresponding input differential-mode voltage and input common-mode voltage, and the positive output signal and the negative output signal have a corresponding output differential-mode voltage and output common-mode voltage, and the amplifier circuit includes: an amplifying unit, configured to receive the positive input signal and the negative input signal and generate the positive output signal and the negative output signal; and an attenuation unit, including: a positive common-mode capacitor and a negative common-mode capacitor, configured to attenuate the input common-mode voltage below a first specific frequency.

Abstract: The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

Abstract: The present application discloses a transconductance amplifier and a related chip. The transconductance amplifier is configured to generate an output current according to a positive input voltage and a negative input voltage, wherein the transconductance amplifier includes: an input stage, configured to receive the positive input voltage and the negative input voltage and generate a positive output current and a negative output current, wherein the input stage includes: a first transistor, wherein a gate thereof is coupled to the positive input voltage; a second transistor, wherein a gate thereof is coupled to the negative input voltage; a first resistor, serially connected between the first transistor and the second transistor; a third transistor, wherein a source of the third transistor is coupled between the first resistor and the first transistor, and a drain of the third transistor is configured to output the positive output current; and a fourth transistor.

Abstract: The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

Abstract: The present application discloses a voltage booster circuit and a related circuit, chip and wearable device. The voltage booster circuit has an output terminal, which provides an output voltage and a load current. The voltage booster circuit includes: a first charge pump, which provides a first bias current; a second charge pump, which provides the load current; an output voltage fixing circuit, which draws the first bias current from the first charge pump to the output terminal, wherein the output voltage fixing circuit fixes a first charge pump voltage of the first charge pump by fixing the first bias current and further fixes the output voltage based on the fixed first charge pump voltage; and a load current generation circuit, which draws the load current from the second charge pump to the output terminal based on a second charge pump voltage of the second charge pump.

Abstract: The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

Abstract: The present application discloses an ADC (10). The ADC has an A/D conversion operation mode and a measurement operation mode. The ADC includes an input terminal (100), a DAC (104), and an output terminal (102). The input terminal is configured to receive an analog signal. The output terminal is configured to output a digital signal. The DAC includes a plurality of D/A conversion units. When the ADC operates in the A/D conversion operation mode, the ADC is configured to convert the analog signal into the digital signal, and when the ADC operates in the measurement operation mode, the digital signal related to a ratio of a capacitance of the D/A conversion unit to be measured to a total capacitance of the plurality of D/A conversion units.

Abstract: The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

Abstract: The present application discloses a PPG circuit, a biological characteristics detection device and a biological characteristics detection method. The PPG circuit is configured to control a light source and N photoelectric converters to sense biological characteristics of an object under test; the PPG circuit includes: a transmitting channel, K receiving channels, wherein the N photoelectric converters are divided into K sets of photoelectric converter sets, and the K receiving channels respectively correspond to K sets of photoelectric converter sets; and a controller, configured to control the PPG circuit to operate in a partial sampling phase or an full sampling phase, so as to generates J or K biological characteristics sampling results during each of the pulse repetition cycles.

Abstract: The present application discloses a voltage booster circuit and a related circuit, chip and wearable device. The voltage booster circuit has an output terminal, which provides an output voltage and a load current. The voltage booster circuit includes: a first charge pump, which provides a first bias current; a second charge pump, which provides the load current; an output voltage fixing circuit, which draws the first bias current from the first charge pump to the output terminal, wherein the output voltage fixing circuit fixes a first charge pump voltage of the first charge pump by fixing the first bias current and further fixes the output voltage based on the fixed first charge pump voltage; and a load current generation circuit, which draws the load current from the second charge pump to the output terminal based on a second charge pump voltage of the second charge pump.

Abstract: The present application discloses a transconductance amplifier and a related chip.

Abstract: The present application discloses an amplifier circuit, a chip and an electronic device, which generates a positive output signal and a negative output signal according to a positive input signal and a negative input signal, wherein the positive input signal and the negative input signal have a corresponding input differential-mode voltage and input common-mode voltage, and the positive output signal and the negative output signal have a corresponding output differential-mode voltage and output common-mode voltage, and the amplifier circuit includes: an amplifying unit, configured to receive the positive input signal and the negative input signal and generate the positive output signal and the negative output signal; and an attenuation unit, including: a positive common-mode capacitor and a negative common-mode capacitor, configured to attenuate the input common-mode voltage below a first specific frequency.

Abstract: The present application discloses an ADC (10). The ADC has an A/D conversion operation mode and a measurement operation mode. The ADC includes an input terminal (100), a DAC (104), and an output terminal (102). The input terminal is configured to receive an analog signal. The output terminal is configured to output a digital signal. The DAC includes a plurality of D/A conversion units. When the ADC operates in the A/D conversion operation mode, the ADC is configured to convert the analog signal into the digital signal, and when the ADC operates in the measurement operation mode, the digital signal related to a ratio of a capacitance of the D/A conversion unit to be measured to a total capacitance of the plurality of D/A conversion units.

Abstract: An operational amplifier includes: a first amplifier stage, configured to generate first output voltages according to first input voltages; a second amplifier stage, configured to generate second output voltages according to the first output voltages; a second output stage circuit, configured to replicate an equivalent or a scaled-down version of the first output stage circuit; a first common-mode feedback circuit, configured to keep an output common-mode voltage of the second output stage circuit at a predetermined value; a logic loop circuit configured to, when the operational amplifier operates in a direct current calibration phase, adjust a difference between the first output voltages; a bias circuit, configured to generate a voltage close to a common-mode voltage of the first output voltages produced after the operational amplifier is turned on, the voltage serving as a reference voltage of a second common-mode feedback circuit.