Abstract: A semiconductor device includes a first region and a second region, and the second region surrounds the first region. The semiconductor device includes at least one electronic unit, a redistribution structure, a plurality of first pads, and a plurality of second pads. The redistribution structure may be electrically connected to at least one electronic unit. A plurality of first pads are arranged on the redistribution structure and correspondingly to the first region. There is a first pitch between two adjacent first pads. A plurality of second pads are arranged on the redistribution structure and correspondingly to the second region. There is a second pitch between two adjacent second pads, so that the first pitch is smaller than the second pitch.

Abstract: The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.

Abstract: A display device including at least two light source modules and a display control substrate is provided. Each of the at least two light source substrates has a first surface and a second surface opposite to each other and includes a plurality of light emitting elements and a plurality of connection pads. The light emitting elements are located on the second surface, and the connection pads are located on the first surface and are electrically connected to the light emitting elements. The display control substrate includes a back plate and a plurality of control elements. The control elements are located on the back plate, part of the control elements are electrically connected to the connection pads to drive and control the light emitting elements, and the second surface of each of the at least two light source substrates forms a part of a display surface of the display device.

Abstract: The present application discloses an amplifier circuit, a chip and an electronic device, which generates a positive output signal and a negative output signal according to a positive input signal and a negative input signal, wherein the positive input signal and the negative input signal have a corresponding input differential-mode voltage and input common-mode voltage, and the positive output signal and the negative output signal have a corresponding output differential-mode voltage and output common-mode voltage, and the amplifier circuit includes: an amplifying unit, configured to receive the positive input signal and the negative input signal and generate the positive output signal and the negative output signal; and an attenuation unit, including: a positive common-mode capacitor and a negative common-mode capacitor, configured to attenuate the input common-mode voltage below a first specific frequency.

Abstract: The present application discloses a transconductance amplifier and a related chip. The transconductance amplifier is configured to generate an output current according to a positive input voltage and a negative input voltage, wherein the transconductance amplifier includes: an input stage, configured to receive the positive input voltage and the negative input voltage and generate a positive output current and a negative output current, wherein the input stage includes: a first transistor, wherein a gate thereof is coupled to the positive input voltage; a second transistor, wherein a gate thereof is coupled to the negative input voltage; a first resistor, serially connected between the first transistor and the second transistor; a third transistor, wherein a source of the third transistor is coupled between the first resistor and the first transistor, and a drain of the third transistor is configured to output the positive output current; and a fourth transistor.

Abstract: The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

Abstract: The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

Abstract: The present application discloses a voltage booster circuit and a related circuit, chip and wearable device. The voltage booster circuit has an output terminal, which provides an output voltage and a load current. The voltage booster circuit includes: a first charge pump, which provides a first bias current; a second charge pump, which provides the load current; an output voltage fixing circuit, which draws the first bias current from the first charge pump to the output terminal, wherein the output voltage fixing circuit fixes a first charge pump voltage of the first charge pump by fixing the first bias current and further fixes the output voltage based on the fixed first charge pump voltage; and a load current generation circuit, which draws the load current from the second charge pump to the output terminal based on a second charge pump voltage of the second charge pump.

Abstract: The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

Abstract: The present application discloses an ADC (10). The ADC has an A/D conversion operation mode and a measurement operation mode. The ADC includes an input terminal (100), a DAC (104), and an output terminal (102). The input terminal is configured to receive an analog signal. The output terminal is configured to output a digital signal. The DAC includes a plurality of D/A conversion units. When the ADC operates in the A/D conversion operation mode, the ADC is configured to convert the analog signal into the digital signal, and when the ADC operates in the measurement operation mode, the digital signal related to a ratio of a capacitance of the D/A conversion unit to be measured to a total capacitance of the plurality of D/A conversion units.

Abstract: The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

Abstract: The present application discloses a PPG circuit, a biological characteristics detection device and a biological characteristics detection method. The PPG circuit is configured to control a light source and N photoelectric converters to sense biological characteristics of an object under test; the PPG circuit includes: a transmitting channel, K receiving channels, wherein the N photoelectric converters are divided into K sets of photoelectric converter sets, and the K receiving channels respectively correspond to K sets of photoelectric converter sets; and a controller, configured to control the PPG circuit to operate in a partial sampling phase or an full sampling phase, so as to generates J or K biological characteristics sampling results during each of the pulse repetition cycles.

Abstract: The present application discloses a voltage booster circuit and a related circuit, chip and wearable device. The voltage booster circuit has an output terminal, which provides an output voltage and a load current. The voltage booster circuit includes: a first charge pump, which provides a first bias current; a second charge pump, which provides the load current; an output voltage fixing circuit, which draws the first bias current from the first charge pump to the output terminal, wherein the output voltage fixing circuit fixes a first charge pump voltage of the first charge pump by fixing the first bias current and further fixes the output voltage based on the fixed first charge pump voltage; and a load current generation circuit, which draws the load current from the second charge pump to the output terminal based on a second charge pump voltage of the second charge pump.

Abstract: The present application discloses a transconductance amplifier and a related chip.

Abstract: The present application discloses an amplifier circuit, a chip and an electronic device, which generates a positive output signal and a negative output signal according to a positive input signal and a negative input signal, wherein the positive input signal and the negative input signal have a corresponding input differential-mode voltage and input common-mode voltage, and the positive output signal and the negative output signal have a corresponding output differential-mode voltage and output common-mode voltage, and the amplifier circuit includes: an amplifying unit, configured to receive the positive input signal and the negative input signal and generate the positive output signal and the negative output signal; and an attenuation unit, including: a positive common-mode capacitor and a negative common-mode capacitor, configured to attenuate the input common-mode voltage below a first specific frequency.

Abstract: The present application discloses an ADC (10). The ADC has an A/D conversion operation mode and a measurement operation mode. The ADC includes an input terminal (100), a DAC (104), and an output terminal (102). The input terminal is configured to receive an analog signal. The output terminal is configured to output a digital signal. The DAC includes a plurality of D/A conversion units. When the ADC operates in the A/D conversion operation mode, the ADC is configured to convert the analog signal into the digital signal, and when the ADC operates in the measurement operation mode, the digital signal related to a ratio of a capacitance of the D/A conversion unit to be measured to a total capacitance of the plurality of D/A conversion units.

Abstract: An operational amplifier includes: a first amplifier stage, configured to generate first output voltages according to first input voltages; a second amplifier stage, configured to generate second output voltages according to the first output voltages; a second output stage circuit, configured to replicate an equivalent or a scaled-down version of the first output stage circuit; a first common-mode feedback circuit, configured to keep an output common-mode voltage of the second output stage circuit at a predetermined value; a logic loop circuit configured to, when the operational amplifier operates in a direct current calibration phase, adjust a difference between the first output voltages; a bias circuit, configured to generate a voltage close to a common-mode voltage of the first output voltages produced after the operational amplifier is turned on, the voltage serving as a reference voltage of a second common-mode feedback circuit.

Abstract: The application provides a charge pump circuit, includes a digital control circuit, coupled to the switch module, configured to receive a up digital signal and a down digital signal, and adjust a first output voltage to a voltage level of an input voltage and adjust an second output voltage to a ground voltage level according to the up digital signal and the down digital signal; a digital-to-analog converter (DAC), configured to generate a corresponding up reference voltage and a corresponding down reference voltage according to the up digital signal and the down digital signal; and a voltage follower, comprising a plurality of operational amplifiers and a plurality of transistor switches, configured to lock the first output voltage and the second output voltage according to the up reference voltage and the down reference voltage; wherein the up digital signal and the down digital signal are varied with time.

Abstract: The present application provides a vector quantization digital-to-analog conversion circuit, for converting a digital signal to an analog signal, characterized by includes a vector quantization circuit, configured to receive the digital signal and generate a vector quantization signal; a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.