Abstract: A reference voltage generating circuit includes: a first capacitor; a second capacitor; a reference voltage sampling capacitor; a first switch for alternatively coupling the second capacitor to a predetermined voltage to allow the second capacitor to sample the predetermined voltage; a second switch for alternatively coupling the second capacitor to the first capacitor to allow the second capacitor to redistribute charges with the first capacitor in order to generate the reference voltage; and a third switch for alternatively coupling the first capacitor to the reference voltage sampling capacitor to allow the reference voltage sampling capacitor to redistribute charges with the first capacitor in order to output the reference voltage.

Abstract: An Audio Codec which comprises a power selecting circuit an audio compiler circuit and a control amplifier circuit. The power selecting circuit receives at least a primary power source and an auxiliary power source and outputs a working power selected from the power sources. The auxiliary power source is selected and output to the control amplifier circuit only when the computer is at a power-off status. When the computer is power-on, the primary power source will be selected and output to both the audio compiler circuit and the control amplifier circuit. Therefore, the Audio Codec of the present invention only needs one set of internally furnished control amplifier circuit to both operate on the normal power-on status and perform the Power OFF CD function.

Abstract: A reference voltage generating circuit includes: a first capacitor; a second capacitor; a reference voltage sampling capacitor; a first switch for alternatively coupling the second capacitor to a predetermined voltage to allow the second capacitor to sample the predetermined voltage; a second switch for alternatively coupling the second capacitor to the first capacitor to allow the second capacitor to redistribute charges with the first capacitor in order to generate the reference voltage; and a third switch for alternatively coupling the first capacitor to the reference voltage sampling capacitor to allow the reference voltage sampling capacitor to redistribute charges with the first capacitor in order to output the reference voltage.

Abstract: A fractional frequency synthesizer, applied to a phase-locked loop, includes a phase detector, a loop filter, a controllable oscillator, a first frequency divider, and a sigma-delta modulator (SDM). The phase detector generates a phase difference signal according to a reference signal and a feedback signal. The loop filter filters the phase difference signal to generate a filtered signal. The controllable oscillator generates the frequency signal according to the filtered signal. The first frequency divider generates the feedback signal by dividing a frequency of the frequency signal according to a dividing factor. The SDM determines the dividing factor according to a control signal.

Abstract: An audio converting device including a digital high-pass filter, an expander, a digital low-pass filter, a delta-sigma modulator, a digital-to-analog converter, an analog low-pass filter and a gain control unit is provided. The digital high-pass filter in this invention can filter out a direct-current component of digital audio data such that the production of noise is avoided when the volume is adjusted by users.

Abstract: A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.

Abstract: An application circuit and method for shaping noises are provided. In an embodiment, an analog-to-digital converter converts a first analog signal into an n-bit digital signal for an encoder to generate a p-bit digital signal. Then a control circuit generates a plurality of control signals based on the p-bit digital signal, wherein p is two to the power of n minus one, and n is an integer greater than one. Each of the (2n?1) unit elements with element mismatch in an internal n-bit digital-to-analog converter executes the digital to analog conversion in response to the corresponding control signal, thereby generating a second analog signal, and an adder outputs the first analog signal based on the second analog signal and a third analog signal.

Abstract: An amplifier circuit having a high time constant. An operational amplifier includes a non-converting input terminal coupled to a ground, a converting input terminal and an output terminal. A first resistor network including at least one stage is coupled between the converting input terminal and the output terminal. Each stage of the first resistor network includes a first node, a first current path and a second current path connected to the first node. The first current path of each stage of the first resistor network is connected to the first node of the next stage, the second current path of each stage of the first resistor network is grounded, and the first current path of the first stage of the first resistor network is connected to the converting input terminal. A loading unit is coupled between the converting input terminal and the output terminal.

Abstract: An amplifier includes a subtracting unit for generating an error signal according to an input signal and an output signal; a noise shaping unit for executing a noise shaping operation on the error signal to produce a noise-shaped signal; a pulse adjustment unit for generating a control signal according to the noise-shaped signal and the input signal; and a power stage for generating the output signal according to the control signal.

Abstract: A pipeline ADC has a plurality of analog-to-digital conversion units cascaded in series to form a pipeline. An error correcting method for the pipeline ADC includes during a first mode, measuring the plurality of analog-to-digital conversion units utilizing an extra analog-to-digital conversion module; calculating a plurality of correction constant sets according to digital output values of the extra analog-to-digital conversion module in the measuring step; and during a second mode, correcting output signals of the plurality of analog-to-digital conversion units according to the correction constant sets.

Abstract: The variable gain amplifier of the present invention includes at least an operation amplifier. By choosing one of output stages, a feedback resistor is selected and the gain of the variable gain amplifier is decided according to the resistance of the selected feedback resistor, as desired. By adjusting the gain of the variable gain amplifier, the received signals can be amplified or attenuated in accordance with design requirement. The variable gain amplifier can include a two-stage architecture, in which a first stage is used for coarse gain adjustment and a second stage is used for fine gain adjustment. The gain of the two-stage variable gain amplifier can be easily adjusted to a desired value.

Abstract: A pipeline ADC includes a pipeline structure having a plurality of analog-to-digital converting units cascaded in series; and a correcting unit coupled to the pipeline structure for correcting an output value of the pipeline structure according to a set of calibration constants. One of the analog-to-digital converting units contains a capacitor switching circuit. During error measurement of the pipeline ADC, the capacitor switching circuit switches to change capacitance allocation of the analog-to-digital converting unit so as to obtain the set of calibration constants.

Abstract: The line driver with active termination includes: a differential amplifier having an inverting output terminal, a non-inverting output terminal, an inverting input terminal, and a non-inverting input terminal; a first resistor unit coupled to the inverting input terminal; a impedance matching resistor unit coupled to the non-inverting output terminal; and a resistive feedback network, having a plurality of resistors in symmetric configuration. The resistive feedback network further includes: a second resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; a third resistor unit coupled to the non-inverting output terminal and the inverting input terminal; a fourth resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; and a fifth resistor unit coupled to the inverting output terminal and the inverting input terminal.

Abstract: An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

Abstract: A system for heating a load-lock chamber, particularly that of a plasma etching system for etching semiconductor wafer substrates. The load-lock chamber heating system includes a heater that is provided in fluid communication with a gas supply which contains an inert gas such as nitrogen. A gas pump pumps the gas from the gas supply through the heater, and from the heater into the load-lock chamber. The gas heats the load-lock chamber to prevent or minimize condensation of corrosive etching gases onto the interior surfaces of the load-lock chamber as well as the surfaces of substrates contained therein.

Abstract: A pipeline ADC for converting an analog input signal to a digital output signal includes: a plurality of analog-to-digital converting units cascading in series to form a pipeline including a plurality of digital output ends; a calculation unit coupled to the analog-to-digital converting units for generating a plurality of calibration parameters in a first mode according to signals at the digital output ends; and a calibration unit coupled to the calculation unit and the analog-to-digital converting units for calibrating signals at the digital output ends in a second mode according to the calibration parameters, so as to generate the digital output signal.

Abstract: A pipeline ADC includes a pipeline structure having a plurality of analog-to-digital converting units cascaded in series; and a correcting unit coupled to the pipeline structure for correcting an output value of the pipeline structure according to a set of calibration constants. One of the analog-to-digital converting units contains a capacitor switching circuit. During error measurement of the pipeline ADC, the capacitor switching circuit switches to change capacitance allocation of the analog-to-digital converting unit so as to obtain the set of calibration constants.

Abstract: A pipeline ADC has a plurality of analog-to-digital conversion units cascaded in series to form a pipeline. An error correcting method for the pipeline ADC includes during a first mode, measuring the plurality of analog-to-digital conversion units utilizing an extra analog-to-digital conversion module; calculating a plurality of correction constant sets according to digital output values of the extra analog-to-digital conversion module in the measuring step; and during a second mode, correcting output signals of the plurality of analog-to-digital conversion units according to the correction constant sets.

Abstract: The present invention offers an over-sampling digital-to-analog converter with variable sampling frequencies to process input signals of variable sampling frequencies. The over-sampling digital-to-analog converter comprises an expander, which expands said input signals with a fixed rate of M to produce over-sampling signals; a digital low-pass filter, which filters out high-frequency ingredients of over-sampling signals and then outputs data with a first rate; a data buffer, which receives the outputted data by said digital low-pass filter with the first rate and outputs the data with a second rate; a modulator, which reads data in said data buffer with the second rate and modulates the data; a digital-to-analog converter, which converts the modulated data to analog signals; and an analog low-pass filter, which filters out high-frequency ingredients of said analog signals for producing output signals.

Abstract: The variable gain amplifier of the present invention includes at least an operation amplifier. By choosing one of output stages, a feedback resistor is selected and the gain of the variable gain amplifier is decided according to the resistance of the selected feedback resistor, as desired. By adjusting the gain of the variable gain amplifier, the received signals can be amplified or attenuated in accordance with design requirement. The variable gain amplifier can include a two-stage architecture, in which a first stage is used for coarse gain adjustment and a second stage is used for fine gain adjustment. The gain of the two-stage variable gain amplifier can be easily adjusted to a desired value.