Abstract: The present invention discloses a watertight monitoring device and comprises: fixing frame, a watertight cover, an image-capturing module, an upper cover, at least an adjustment tab, at least a plastic film, a front cover, and a rear cover; wherein the fixing frame has an outer surface provided with a recess having at least a through hole, the plastic film having an end coupled with the bottom edge of the adjustment tab and an opposite end passing sequentially through the aperture of the watertight cover and the through hole of the recess on the outer surface of the fixing frame and coupled with the adjustment rod of the image-capturing module, wherein the projecting portion of the adjustment tab can be pushed along the outer surface of the monitoring device so that the adjustment tab is moved in the arc direction, and the plastic film thus driving the adjustment rod of the image-capturing module so as to adjust functions of the image-capturing module.

Abstract: A switching mechanism for a camera device includes a driving device, a first screw bar connecting to the driving device, a second screw bar connecting to the first screw bar, and a lead screw having an end coupled with the second screw bar. The first screw bar is driven by the driving device via a screw thread thereof, and the second screw bar is driven by the first screw bar via a screw thread thereof, thereby driving the lead screw for rotation. The screw nut is disposed on the lead screw and moved back and forth via the rotation of the lead screw. Two stop blocks disposed at two ends of the lead screw respectively are to limit two positions of the moved screw nut while the screw nut is moved beyond a threaded area of the lead screw, upon which time the screw nut is slightly engaged with the lead screw.

Abstract: An apparatus and method of automatic identification an external audio input/output device. The external device connected to an audio jack is identified as an audio output or input device, according to the impedance thereof. Furthermore, the present invention automatically selects the most suitable internal circuit to connect to the external device.

Abstract: A sigma-delta modulator and an output rate reduction method are disclosed. The sigma-delta modulator comprises an integrator, an analog-to-digital converter, and a controller. An input signal is received by the integrator to generate an integrated signal. The integrated signal is then converted by the analog-to-digital converter into a digital modulation signal. The input signal is received by the controller to calculate an input signal power. The analog-to-digital converter can be controlled by the controller based on a predetermined power value and a sum of the input signal power and a total quantization error power. By the way mentioned above, the out rate of the sigma-delta modulator is reduced.

Abstract: A signal processing system for changing a level of an input signal to generate an output signal is disclosed. The signal processing system includes a shifter, a sigma-delta modulator, and a level adjuster. The shifter is utilized for receiving the input signal and for bit-shifting the input signal according to a first predetermined gain to generate a first adjustment signal. The sigma-delta modulator is utilized for generating the output signal according a second adjustment signal and the first adjustment. The level adjuster is utilized for adjusting a level of the output signal according to a second predetermined gain to generate the second adjustment signal.

Abstract: A fractional frequency synthesizer, applied to a phase-locked loop, includes a phase detector, a loop filter, a controllable oscillator, a first frequency divider, and a sigma-delta modulator (SDM). The phase detector generates a phase difference signal according to a reference signal and a feedback signal. The loop filter filters the phase difference signal to generate a filtered signal. The controllable oscillator generates the frequency signal according to the filtered signal. The first frequency divider generates the feedback signal by dividing a frequency of the frequency signal according to a dividing factor. The SDM determines the dividing factor according to a control signal.

Abstract: A sigma-delta modulator is disclosed. The sigma-delta modulator includes a first integrator, a second integrator, an analog-to-digital converter, a digital-to-analog converter (DAC), and a compensating device. The first integrator receives an input signal for generating a first output signal. The second integrator receives the first output signal for generating a second output signal. The ADC converts the second output signal into a digital modulation signal. The DAC converts the digital modulation signal into an analog feedback signal. The analog feedback signal is transmitted to the first integrator and the second integrator. The compensating device is for compensating the analog feedback signal for a time delay caused by a feedback loop from the ADC through the DAC to the first integrator.

Abstract: An apparatus includes a first trigger, a second trigger, a pulse generator, and a control unit. The first trigger generates a first trigger signal and a first level signal; the second trigger generates a second trigger signal and a second level signal; the pulse generator generates a digital output signal according to the first and the second level signals; and the control unit outputs the first and the second control voltages according to the digital input signal and the digital output signal.

Abstract: A data weighted average circuit is disclosed which includes a lookup unit and a storage unit. The invention uses a lookup table to speed up the circuit operation. Besides, the operation delay is not affected by various orders of the data weighted average circuit and various bit-widths of input data.

Abstract: A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.

Abstract: A composite shadow ring that is constructed of an upper ring and a lower ring assembled together by a plurality of dowel pins and a method for using the ring. The upper ring and the lower ring each has a predetermined outside diameter that is substantially the same, a planar top surface and a planer bottom surface parallel to the planar top surface. Each of the planar bottom surface of the upper ring and the planar top surface of the lower ring has at least two blind holes formed therein. A plurality of dowel pins are used to frictionally engage the at least two blind holes in the upper ring and the at least two blind holes in the lower ring.

Abstract: A sigma-delta modulator and an output rate reduction method are disclosed. The sigma-delta modulator comprises an integrator, an analog-to-digital converter, and a controller. An input signal is received by the integrator to generate an integrated signal. The integrated signal is then converted by the analog-to-digital converter into a digital modulation signal. The input signal is received by the controller to calculate an input signal power. The analog-to-digital converter can be controlled by the controller based on a predetermined power value and a sum of the input signal power and a total quantization error power. By the way mentioned above, the out rate of the sigma-delta modulator is reduced.

Abstract: A jack detection circuit includes a transition circuit and an AD converter. The transition circuit linearizes analog signals sent from a switching circuit. The AD converter converts the linearized analog signals to digital output signals thereby decreasing the complexity of signal recognition.

Abstract: An analog front end circuit is provided, which comprises at least one converting circuit. Each converting circuit further comprises a clamper, a low-pass filter, an input buffer and a sigma-delta analog-to-digital converter. By using the sigma-delta analog to digital converter, the invention not only increases the resolution, but reduces the order of an anti-aliasing filter, therefore reducing the size and the power consumption of the analog circuit.

Abstract: An amplifier includes a subtracting unit for generating an error signal according to an input signal and an output signal; a noise shaping unit for executing a noise shaping operation on the error signal to produce a noise-shaped signal; a pulse adjustment unit for generating a control signal according to the noise-shaped signal and the input signal; and a power stage for generating the output signal according to the control signal.

Abstract: An application circuit for shaping noises and method thereof involve an analog-to-digital converter which converts a first analog signal into an n-bit digital signal for an encoder to generate a p-bit digital signal. Then a control circuit generates a plurality of control signals based on the p-bit digital signal, wherein p is two to the power of n minus one, and n is an integer greater than one. Each of the (2n?1) unit elements with element mismatch in an internal n-bit digital-to-analog converter executes the digital to analog conversion in response to the corresponding control signal, thereby generating a second analog signal, and an adder outputs the first analog signal based on the second analog signal and a third analog signal.

Abstract: An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

Abstract: A sigma-delta modulator is disclosed. The sigma-delta modulator includes a first integrator, a second integrator, an analog-to-digital converter, a digital-to-analog converter (DAC), and a compensating device. The first integrator receives an input signal for generating a first output signal. The second integrator receives the first output signal for generating a second output signal. The ADC converts the second output signal into a digital modulation signal. The DAC converts the digital modulation signal into an analog feedback signal. The analog feedback signal is transmitted to the first integrator and the second integrator. The compensating device is for compensating the analog feedback signal for a time delay caused by a feedback loop from the ADC through the DAC to the first integrator.

Abstract: An apparatus includes a first trigger, a second trigger, a pulse generator, and a control unit. The first trigger generates a first trigger signal and a first level signal; the second trigger generates a second trigger signal and a second level signal; the pulse generator generates a digital output signal according to the first and the second level signals; and the control unit outputs the first and the second control voltages according to the digital input signal and the digital output signal.

Abstract: A signal processing system for changing a level of an input signal to generate an output signal is disclosed. The signal processing system includes a shifter, a sigma-delta modulator, and a level adjuster. The shifter is utilized for receiving the input signal and for bit-shifting the input signal according to a first predetermined gain to generate a first adjustment signal. The sigma-delta modulator is utilized for generating the output signal according a second adjustment signal and the first adjustment. The level adjuster is utilized for adjusting a level of the output signal according to a second predetermined gain to generate the second adjustment signal.