Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.

Abstract: A modulation device includes a substrate, an electrostatic discharge protection element, an electronic element, and a driving element. The substrate has an active region. The electrostatic discharge protection element is arranged around the active region. The electronic element is disposed in the active region. The driving element is electrically connected to the electronic element.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a lower horizontal supporting layer, an upper horizontal supporting layer, a vertical supporting structure, and a first capacitor electrode. The lower horizontal supporting layer is disposed on the substrate. The upper horizontal supporting layer is disposed on the lower horizontal supporting layer. The vertical supporting structure extends between the lower horizontal supporting layer and the upper horizontal supporting layer. The first capacitor electrode is disposed on the substrate and extends from the lower horizontal supporting layer to the upper horizontal supporting layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a lower horizontal supporting layer, an upper horizontal supporting layer, a vertical supporting structure, and a first capacitor electrode. The lower horizontal supporting layer is disposed on the substrate. The upper horizontal supporting layer is disposed on the lower horizontal supporting layer. The vertical supporting structure extends between the lower horizontal supporting layer and the upper horizontal supporting layer. The first capacitor electrode is disposed on the substrate and extends from the lower horizontal supporting layer to the upper horizontal supporting layer.

Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a series of sensing operations respectively corresponding to a plurality of sensing voltages, wherein a sensing voltage of a specific sensing operation of the series of sensing operations has a sensing voltage determined according to a result of an initial sensing operation of the series of sensing operations; determining a threshold voltage of the Flash cell according to at least a digital value generated by the series of sensing operations; and using the determined threshold voltage to perform soft decoding of the Flash cell.

Abstract: A portable electronic device including a first body, a second body, a pivot element, a heat source, a first flexible heat conductive element, and a flip cover is provided. The pivot element is connected to the second body, and the second body is pivotally connected to the first body through the pivot element. The heat source is disposed in the first body. The first flexible heat conductive element is thermally coupled to the heat source and extends toward the pivot element from the heat source. The first flexible heat conductive element passes through the pivot element and extends into the inside of the second body and is thus thermally coupled to the second body. The flip cover is pivotally connected to the first body and located on a moving path of the pivot element.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.

Abstract: A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.

Abstract: The present invention provides a filtering circuit comprising a poly phase filter and a quadrature phase detector. The poly phase filter comprises a first path, a second path, a third path and a fourth path. The first path is configured to receive a first input signal to generate a first clock signal. The second path comprising a first adjustable delay circuit is configured to receive the first input signal to generate a second clock signal. The third path comprising a second adjustable delay circuit is configured to receive a second input signal to generate a third clock signal. The fourth path is configured to receive the second input signal to generate a fourth clock signal. The quadrature phase detector is configured to detect phases of these clock signals to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit.

Abstract: The present invention relates to a network connection system. The network connection system includes a gateway, an extender, and a wireless access point. Wherein, the gateway can be used as one of the enrollee router and the registrar router, and the extender can be used as the other of the enrollee router and the registrar router, and the extender can send authentication information to the gateway. After the gateway confirms that the extender is a model supported by the gateway according to the authentication information, the gateway sends a credential to the extender, allowing the extender to establish a wireless mesh network through the wireless access point. In this way, the purpose of seamless connection is achieved. In addition, the network connection system of the present invention has functions such as high security and convenience.

Abstract: The present invention provides a transmitter including a first variable resistor, a first transistor, a second transistor, a third transistor and a fourth transistor is disclosed. The first variable resistor is coupled between a supply voltage and a first node. A first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to a first output terminal of the transmitter. A first electrode of the second transistor is coupled to the first output terminal of the transmitter, and a second electrode of the second transistor is coupled to a second node. A first electrode of the third/fourth transistor is coupled to the first node, and a second electrode of the third/fourth transistor is coupled to a second output terminal of the transmitter.

Abstract: The present application provides a memory device having a double-sided capacitor. The memory device includes a semiconductor substrate; a capacitor protruding from the semiconductor substrate; a first supporting layer disposed on the semiconductor substrate and surrounding the capacitor; and a second supporting layer disposed above the first supporting layer and surrounding the capacitor, wherein the second supporting layer includes a first opening extending through the second supporting layer and disposed adjacent to the capacitor.

Abstract: The present application provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate; disposing a first supporting layer over the semiconductor substrate; disposing a first molding layer over the first supporting layer; disposing a second supporting layer over the first molding layer; removing a portion of the second supporting layer to form a first opening; disposing a second molding layer over the second supporting layer and within the first opening; forming a trench extending through the first supporting layer, the first molding layer, the second supporting layer and the second molding layer; disposing a conductive layer conformal to the trench; and removing the first molding layer and the second molding layer.

Abstract: The present invention provides a filtering circuit comprising a poly phase filter and a quadrature phase detector. The poly phase filter comprises a first path, a second path, a third path and a fourth path. The first path is configured to receive a first input signal to generate a first clock signal. The second path comprising a first adjustable delay circuit is configured to receive the first input signal to generate a second clock signal. The third path comprising a second adjustable delay circuit is configured to receive a second input signal to generate a third clock signal. The fourth path is configured to receive the second input signal to generate a fourth clock signal. The quadrature phase detector is configured to detect phases of these clock signals to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit.

Abstract: The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.

Abstract: A class-D amplifier with good signal-to-noise ratio (SNR) performance is shown. The class-D amplifier includes a loop filter, a pulse-width modulation signal generator, a gate driver, a power driver, and a feedback circuit, which are configured to establish a closed amplification loop. The feedback circuit is configured to establish a feedback path. The class-D amplifier further includes a feedback breaker. The feedback breaker breaks the feedback path in response to conditions in which there no-signal information in the class-D amplifier.

Abstract: An amplification circuit with a common-mode voltage compensation circuit is shown. The common-mode voltage compensation circuit has a first compensation resistor coupled between an input terminal of a loop filter of the amplification circuit and a control node, and a second compensation resistor coupled between another input terminal of the loop filter and the control node. The control node is coupled to a power ground voltage when the two output signals of the amplification circuit are high, and it is coupled to a power supply voltage when the two output signals of the amplification circuit are low.

Abstract: A filter circuit includes a polyphase filter used to generate a plurality of output signals with different phases according to a plurality of input signals. The polyphase filter includes a switch circuit and a feed-forward capacitor. The switch circuit has a control terminal used to receive a control voltage, a first connection terminal used to output one of the output signals, and a second connection terminal used to receive one of the input signals. The feed-forward capacitor has a first plate coupled to the second connection terminal of the switch circuit and a second plate coupled to the control terminal of the switch circuit.

Abstract: A network path selection method and a network node device using the same are disclosed. The network path selection method includes: determining whether a first uplink time parameter table is received from the first relay node device and whether a second uplink time parameter table is received from the second relay node device; when the first uplink time parameter table is received from the first relay node device and the second uplink time parameter table is received from the second relay node device, calculating a first estimated uplink time parameter according to the first uplink time parameter table and a second estimated uplink time parameter according to the second uplink time parameter table; and determining to connect to a gateway via one of the first relay node device and the second relay node device according to the first estimated uplink time parameter and the second estimated uplink time parameter.