Patents by Inventor Wen-Chih Chen
Wen-Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240145431Abstract: A method includes: attaching a first die and a second die to a substrate, the first die comprising a conductive via; forming a die spacer between the first die and the second die; thinning the first die and the second die, wherein after thinning the first die and the second die, the die spacer protrudes a first height above an upper surface of the first die; depositing an insulating layer over the first die and the second die; planarizing the insulating layer, wherein after planarizing, the insulating layer has a first thickness above the first die and a second thickness above the die spacer; attaching a third die and a fourth die to the first die and the second die; and attaching a support substrate to the third die and the fourth die.Type: ApplicationFiled: January 6, 2023Publication date: May 2, 2024Inventors: Yung-Lung Chen, Ming-Yun Liao, Yi-Hsiu Chen, Wen-Chih Chiou
-
Publication number: 20240136324Abstract: A semiconductor manufacturing method is provided. The semiconductor manufacturing method includes the following steps. A first semiconductor element with a bonding film and a first stressing film is formed. The first bonding film and the first stressing film are formed on two opposite sides of the first semiconductor element. The first stressing film makes the first bonding film to have a first convex surface. A second semiconductor element with a second bonding film is formed. The second bonding film is formed on one side of the second semiconductor element. The first semiconductor element and the second semiconductor element are bonded by bonding the first bonding film and the second bonding film.Type: ApplicationFiled: January 19, 2023Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chih CHIOU, Yen-Ming CHEN, Yung-Chi LIN
-
Publication number: 20240133427Abstract: An air-floating guide rail device includes a guide rail unit, a slider unit, and a linear motor unit. The guide rail unit includes a guide rail body and two air-floating block sets made of a material different from that of the guide rail body and each including top and side air-floating blocks. The slider unit includes a main sliding seat and two lateral sliding seats connected integrally to the main sliding seat and each having first and second guiding surfaces transverse to each other and disposed respectively adjacent to corresponding top and side air-floating blocks, and first and second air guiding passages connecting the first and second guiding surfaces to the external environment. The linear motor unit includes a stator and a mover mounted fixedly to the main sliding seat and movable relative to the stator for driving linear movement of the slider unit relative to the guide rail unit.Type: ApplicationFiled: December 20, 2022Publication date: April 25, 2024Inventors: KUN-CHENG TSENG, KUEI-TUN TENG, WEI-CHIH CHEN, WEN-CHUNG LIN
-
Patent number: 11964409Abstract: A multi-shot moulding part structure includes a first structural part, an ink decoration layer, and a second structural part. The first structural part has a first area surface, a second area surface, and a joining surface located on the second area surface. The joining surface is non-parallel to the second area surface. The ink decoration layer is spread on the first area surface and the second area surface, but not on the joining surface. The second structural part is combined with the first structural part and covers the second area surface. The second structural part touches the joining surface. By the second structural part touching the joining surface of the first structural part that is not coated with the ink decoration layer, the structural bonding strength between the first structural part and the second structural part is enhanced.Type: GrantFiled: August 31, 2021Date of Patent: April 23, 2024Assignees: Inventec (Pudong) Technology Corp., Inventec CorporationInventors: Wen-Ching Lin, Ting-Yu Wang, Fa-Chih Ke, Yu-Ling Lin, Wen-Hsiang Chen
-
Patent number: 11965237Abstract: A system and a method for detecting abnormality of a thin-film deposition process are provided. In the method, a thin-film is deposited on a substrate in a thin-film deposition chamber by using a target, a dimension of a collimator mounted between the target and the substrate is scanned by using at least one sensor disposed in the thin-film deposition chamber to derive an erosion profile of the target, and abnormality of the thin-film deposition process is detected by analyzing the erosion profile with an analysis model trained with data of a plurality of erosion profiles derived under a plurality of deposition conditions.Type: GrantFiled: November 13, 2020Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hao Cheng, Hsuan-Chih Chu, Yen-Yu Chen
-
Publication number: 20240125849Abstract: An RF testing method is applied between a testing instrument and multiple devices under test at least including a first DUT and a second DUT. The testing instrument includes a signal generator and a signal analyzer. A sync signal is sent to the testing instrument and the first DUT, so that the first DUT occupies the signal generator to receive a testing signal from the signal generator. The first DUT sends an uplink signal to the signal analyzer based on the testing signal to occupy the signal analyzer for signal analysis at a first point in time. The sync signal is sent to the testing instrument and the second DUT, so that the second DUT occupies the signal generator to receive the testing signal from the signal generator at a second point in time. The first point in time is parallel to the second point in time.Type: ApplicationFiled: March 8, 2023Publication date: April 18, 2024Inventors: Jung-Yin CHIEN, Po-Yen TSENG, Pin-Lin HUANG, Wen-Chih CHEN
-
Publication number: 20240120203Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.Type: ApplicationFiled: March 8, 2023Publication date: April 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Chih HSIUNG, Yun-Hua CHEN, Bing-Sian WU, Yi-Hsuan CHIU, Yu-Wei CHANG, Wen-Kuo HSIEH, Chih-Yuan TING, Huan-Just LIN
-
Publication number: 20240119200Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.Type: ApplicationFiled: October 3, 2023Publication date: April 11, 2024Applicant: MEDIATEK INC.Inventors: Yu-Jen Chen, Chien-Chih Wang, Wen-Wen Hsieh, Ying-Yi Teng
-
Patent number: 11948920Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.Type: GrantFiled: August 30, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
-
Patent number: 11942543Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.Type: GrantFiled: June 29, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
-
Patent number: 11942941Abstract: A device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.Type: GrantFiled: July 26, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chih Ou, Wen-Hao Chen
-
Patent number: 11934763Abstract: A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.Type: GrantFiled: November 9, 2020Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chih Ou, Wen-Hao Chen
-
Patent number: 11935795Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.Type: GrantFiled: July 28, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
-
Patent number: 11928416Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.Type: GrantFiled: March 1, 2023Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chih Ou, Kuo-Fu Lee, Wen-Hao Chen, Keh-Jeng Chang, Hsiang-Ho Chang
-
Publication number: 20240069592Abstract: An enclosure for an electronic device has a staggered materials corner structure. The enclosure includes an integral metal frame defining exterior sides of the enclosure. The integral metal frame has a tab inset and not visible at a corner of the enclosure. The enclosure includes either or both of first and second materials molded around the tab. The tab of the integral metal frame and either or both of the first and second materials define the staggered materials corner structure of the enclosure.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventors: Wen-Chih Chen, Po-Feng Chuang
-
Publication number: 20240074119Abstract: An immersion cooling system includes a pressure seal tank, an electronic apparatus, a pressure balance pipe and a relief valve. The pressure seal tank is configured to store coolant. A vapor space is formed in the pressure seal tank above the liquid level of the coolant. The electronic apparatus is completely immersed in the coolant. The pressure balance pipe has a gas collection length. The first port of the pressure balance pipe is disposed on the top surface of the pressure seal tank. The relief valve is disposed on the second port of the pressure balance pipe. The second port is farther away from the top surface of the pressure seal tank than the first port. The gas collection length of the pressure equalization tube allows the concentration of vaporized coolant at the first port to be greater than the concentration of vaporized coolant at the second port.Type: ApplicationFiled: May 9, 2023Publication date: February 29, 2024Inventors: Ren-Chun CHANG, Wei-Chih LIN, Sheng-Chi WU, Wen-Yin TSAI, Li-Hsiu CHEN
-
METHOD AND SYSTEM OF IMAGE PROCESSING WITH POWER REDUCTION WHILE USING A UNIVERSAL SERIAL BUS CAMERA
Publication number: 20240069619Abstract: A method, system, and article provide image processing with power reduction while using universal serial bus cameras.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Intel CorporationInventors: Ko Han Wu, Thiam Wah Loh, Kenneth K. Lau, Wen-Kuang Yu, Ming-Jiun Chang, Andy Yeh, Wei Chih Chen -
Publication number: 20240074033Abstract: A power module includes a power circuit board, a signal pin, a shielding substrate, and an electrically insulating component. The signal pin is disposed and stands on the power circuit board. The shielding substrate is located above the power circuit board and spaced apart from the power circuit board. The shielding substrate has a first through hole. The signal pin is disposed through the first through hole. The electrically insulating component surrounds the signal pin. The electrically insulating component has a second through hole. The signal pin is disposed through the second through hole. The signal pin is spaced apart from the shielding substrate by a distance by the electrically insulating component.Type: ApplicationFiled: April 18, 2023Publication date: February 29, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventor: Wen-Chih CHEN
-
Patent number: 11901833Abstract: Systems and methods for switching between a power supply mode and an electronic load mode are disclosed. For switching from the power supply mode to the electronic load mode, the method comprises the steps of: deactivating a power element; activating a current control module and a phase-locked loop to obtain a voltage phase of a device under test; calculating a turn-on amount of the power element according to a current setting value and the voltage phase; and causing the power element to generate a load current for the device under test. For switching from the electronic load mode to the power supply mode, the method comprises the steps of: deactivating the power element; activating a voltage control module; calculating the turn-on amount of the power element according to a voltage setting value; and causing the power element to input a corresponding voltage to the device under test.Type: GrantFiled: October 5, 2022Date of Patent: February 13, 2024Assignee: CHROMA ATE INC.Inventors: Cheng Chung Lee, Szu Chieh Su, Wen Chih Chen, Chih Hsing Lin, Jhen Wei Gong
-
Patent number: 11776867Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 ?m and 300 ?m. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.Type: GrantFiled: June 14, 2022Date of Patent: October 3, 2023Assignee: Industrial Technology Research InstituteInventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han