Patents by Inventor Wen-Chih Chiou

Wen-Chih Chiou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Protection layer for adhesive material at wafer edge
    Patent number: 9997440
    Abstract: A three-dimensional integrated circuit (3DIC) including a first substrate having a first surface and a second surface opposite to the first surface and a second substrate attached to the first surface of the first substrate. The 3DIC further includes an interconnect between attached to the first surface of the first substrate and the second substrate and a plurality of through vias formed in the first substrate and electrically coupled to the interconnect. The 3DIC further includes a protection layer over the second surface of the first substrate, wherein each of the plurality of through vias protrudes through the protection layer and a plurality of dies, each die of the plurality of dies attached to at least one through via of the plurality of through vias.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chih Chiou, Weng-Jin Wu, Shau-Lin Shue
  • Through silicon via structure
    Patent number: 9997497
    Abstract: A device includes a through substrate via (TSV) extending through a device substrate. The TSV includes a first conductive material having a sidewall, a protruding end of the TSV protruding from a second side of the device substrate. A liner covers the sidewall of the first conductive material from a below the top surface of the protruding end of the TSV to an opposite end of the TSV. A passivation layer is disposed over the second side of the device substrate and over a portion of the liner disposed on the protruding end of the TSV, the passivation layer having a stair-step surface extending away from the TSV. A conductive interface layer is disposed over the passivation layer, the sidewall of the first conductive material, and the top surface of the protruding end of the TSV. A second conductive material is disposed over the first conductive material.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai
  • Interconnect Structure and Method of Forming Same
    Publication number: 20180145046
    Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 24, 2018
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Through Via Structure and Method
    Publication number: 20180145022
    Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.
    Type: Application
    Filed: November 2, 2017
    Publication date: May 24, 2018
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Robust Through-Silicon-Via Structure
    Publication number: 20180145012
    Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 24, 2018
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Through via structure and method
    Patent number: 9978607
    Abstract: A device comprises a via in a substrate comprising a lower via portion with a first width formed of a first conductive material and an upper via portion with a second width greater than the first width, wherein the upper via portion comprises a protection layer formed of the first conductive material and a via fill material portion formed of a second conductive material.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hung-Pin Chang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Wafer backside interconnect structure connected to TSVs
    Patent number: 9978708
    Abstract: An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Wen-Chih Chiou, Shau-Lin Shue
  • Interconnect structure and method
    Patent number: 9953920
    Abstract: An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first photo-sensitive dielectric layer formed over the interlayer dielectric layer, wherein the first photo-sensitive dielectric layer comprises a first metal structure and a second photo-sensitive dielectric layer formed over the first photo-sensitive dielectric, wherein the second photo-sensitive dielectric layer comprises a second metal structure having a bottom surface coplanar with a top surface of the first metal structure.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yu Chen, Ku-Feng Yang, Tasi-Jung Wu, Lin-Chih Huang, Yuan-Hung Liu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Semiconductor manufacturing process and package carrier
    Patent number: 9922934
    Abstract: A package carrier includes a carrier and a light absorption layer. The light absorption layer is disposed on the carrier. The light absorption layer includes a notch at the periphery of the carrier, and the notch is light transmissive so as to expose the carrier to light in a normal direction of the carrier. A semiconductor manufacturing process is also provided.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Hui Wang, Chih-Hung Cheng, Yung-Chi Lin, Wen-Chih Chiou
  • Semiconductor devices, methods of manufacture thereof, and capacitors
    Patent number: 9899467
    Abstract: Semiconductor devices, methods of manufacture thereof, and capacitors are disclosed. In some embodiments, a semiconductor device includes a first capacitor and a protection device coupled in series with the first capacitor. A second capacitor is coupled in parallel with the first capacitor and the protection device.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chih Chiou, Shin-Puu Jeng, Ebin Liao
  • Bond structures and the methods of forming the same
    Patent number: 9893028
    Abstract: A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Ming-Fa Chen, Yi-Hsiu Chen
  • Method and Structure of Three-Dimensional Chip Stacking
    Publication number: 20180019236
    Abstract: A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 18, 2018
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Yung-Chi Lin
  • Self-Alignment for Redistribution Layer
    Publication number: 20180012825
    Abstract: An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Inventors: Ku-Feng Yang, Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai, Hsin-Yu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Robust through-silicon-via structure
    Patent number: 9865523
    Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Methods for forming a device having a capped through-substrate via structure
    Patent number: 9847256
    Abstract: A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Yen-Hung Chen, Yin-Hua Chen, Ebin Liao, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Chip-stacking apparatus having a transport device configured to transport a chip onto a substrate
    Patent number: 9842823
    Abstract: A chip-stacking apparatus for stacking a chip on a substrate is provided. The chip-stacking apparatus includes a substrate support configured to carry the substrate and a transport device configured to dispose a chip to the substrate. The transport device includes a bond head including a bond base and an attaching element disposed on the bond base and configured to allow the chip to be attached thereon. The center area of the attaching element is higher than an edge area of the attaching element relative to the bond base.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: December 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, HsiaoYun Lo, Yi-Hsiu Chen, Wen-Chih Chiou
  • Through via structure
    Patent number: 9831177
    Abstract: An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive material. The through via further comprises sidewall portions formed of the conductive material and a middle portion formed between the sidewall portions, wherein the middle portion is formed of a dielectric material.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • SEMICONDUCTOR MANUFACTURING PROCESS AND PACKAGE CARRIER
    Publication number: 20170317033
    Abstract: A package carrier includes a carrier and a light absorption layer. The light absorption layer is disposed on the carrier. The light absorption layer includes a notch at the periphery of the carrier, and the notch is light transmissive so as to expose the carrier to light in a normal direction of the carrier. A semiconductor manufacturing process is also provided.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 2, 2017
    Inventors: Shih-Hui Wang, Chih-Hung Cheng, Yung-Chi Lin, Wen-Chih Chiou
  • Structure and Formation Method for Chip Package
    Publication number: 20170317030
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a polymer layer over the semiconductor die and the package layer. The chip package further includes a dielectric layer over the polymer layer. The dielectric layer is substantially made of a semiconductor oxide material. In addition, the chip package includes a conductive feature in the dielectric layer electrically connected to a conductive pad of the semiconductor die.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Chen-Hua Yu, Wen-Chih Chiou
  • Methods of packaging semiconductor devices and packaged semiconductor devices
    Patent number: 9806062
    Abstract: Packaged semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes a substrate and a plurality of integrated circuit dies coupled to the substrate. The device also includes a molding material disposed over the substrate between adjacent ones of the plurality of integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies, wherein the cap layer comprises an electrically conductive material that directly contacts the molding material and each of the plurality of integrated circuit dies.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Wen-Chih Chiou, Tu-Hao Yu, Hung-Jung Tu, Yu-Liang Lin, Shih-Hui Wang