Patents by Inventor Wen-Chih Chiou

Wen-Chih Chiou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CHIP-STACKING APPARATUS
    Publication number: 20160190087
    Abstract: A chip-stacking apparatus for stacking a chip on a substrate is provided. The chip-stacking apparatus includes a substrate support configured to carry the substrate and a transport device configured to dispose a chip to the substrate. The transport device includes a bond head including a bond base and an attaching element disposed on the bond base and configured to allow the chip to be attached thereon. The center area of the attaching element is higher than an edge area of the attaching element relative to the bond base.
    Type: Application
    Filed: December 29, 2014
    Publication date: June 30, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua YU, HsiaoYun LO, Yi-Hsiu CHEN, Wen-Chih CHIOU
  • Through Silicon Via Structure and Method
    Publication number: 20160181157
    Abstract: A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.
    Type: Application
    Filed: February 26, 2016
    Publication date: June 23, 2016
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai
  • Light-emitting diodes on concave texture substrate
    Patent number: 9373755
    Abstract: A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: June 21, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chen-Hua Yu, Hung-Ta Lin, Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu
  • TSV structures and methods for forming the same
    Patent number: 9373575
    Abstract: A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Wen-Chih Chiou, Ku-Feng Yang, Tsang-Jiuh Wu, Jing-Cheng Lin
  • Integrated Circuit Package and Methods of Forming Same
    Publication number: 20160172333
    Abstract: A method for forming integrated circuit packages is presented. A first plurality of first tier stacks are mounted to the substrate, wherein the substrate has one or more contact pads corresponding to each of the first tier stacks and has one or more probing pads associated with each of the first tier stacks. Each of the first tier stacks is electrically tested to identify known good first tier stacks and known bad first tier stacks. A first plurality of stacking substrates are mounted to the known good first tier stacks, thereby forming a plurality of second tier stacks. Each of the second tier stacks is electrically tested to identify known good second tier stacks and known bad second tier stacks.
    Type: Application
    Filed: February 25, 2016
    Publication date: June 16, 2016
    Inventors: Chi-Hsi Wu, Chen-Hua Yu, Hsiang-Fan Lee, Shih-Peng Tai, Tang-Jung Chiu, Wen-Chih Chiou
  • Backside Through Vias in a Bonded Structure
    Publication number: 20160172403
    Abstract: A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set.
    Type: Application
    Filed: February 23, 2016
    Publication date: June 16, 2016
    Inventors: Weng-Jin Wu, Ku-Feng Yang, Hung-Pin Chang, Wen-Chih Chiou, Chen-Hua Yu
  • PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20160118301
    Abstract: A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.
    Type: Application
    Filed: January 8, 2016
    Publication date: April 28, 2016
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Wen-Chih Chiou, Jui-Pin Hung, Der-Chyang Yeh, Chiung-Han Yeh
  • Interconnect Structure and Method of Forming Same
    Publication number: 20160118356
    Abstract: An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer.
    Type: Application
    Filed: January 8, 2016
    Publication date: April 28, 2016
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • CIS chips and methods for forming the same
    Patent number: 9324756
    Abstract: A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Jing-Cheng Lin
  • Bump structure for stacked dies
    Patent number: 9312225
    Abstract: A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Kuo-Ching Hsu, Chen-Shien Chen, Wen-Chih Chiou, Chen-Hua Yu
  • Formation of Through Via Before Contact Processing
    Publication number: 20160099196
    Abstract: The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.
    Type: Application
    Filed: December 7, 2015
    Publication date: April 7, 2016
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Thin wafer handling method
    Patent number: 9305769
    Abstract: A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: April 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Shin-Puu Jeng, Hung-Jung Tu
  • Stacked structures and methods of forming stacked structures
    Patent number: 9299612
    Abstract: A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Through silicon via structure
    Patent number: 9299676
    Abstract: A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai
  • Backside through vias in a bonded structure
    Patent number: 9293418
    Abstract: A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weng-Jin Wu, Ku-Feng Yang, Hung-Pin Chang, Wen-Chih Chiou, Chen-Hua Yu
  • Barrier for through-silicon via
    Patent number: 9287166
    Abstract: A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Through Via Structure and Method
    Publication number: 20160071765
    Abstract: A device comprises a via in a substrate comprising a lower via portion with a first width formed of a first conductive material and an upper via portion with a second width greater than the first width, wherein the upper via portion comprises a protection layer formed of the first conductive material and a via fill material portion formed of a second conductive material.
    Type: Application
    Filed: September 5, 2014
    Publication date: March 10, 2016
    Inventors: Yung-Chi Lin, Hung-Pin Chang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Methods of forming integrated circuit package
    Patent number: 9281254
    Abstract: A method for forming integrated circuit packages is presented. A first plurality of first tier stacks are mounted to the substrate, wherein the substrate has one or more contact pads corresponding to each of the first tier stacks and has one or more probing pads associated with each of the first tier stacks. Each of the first tier stacks is electrically tested to identify known good first tier stacks and known bad first tier stacks. A first plurality of stacking substrates are mounted to the known good first tier stacks, thereby forming a plurality of second tier stacks. Each of the second tier stacks is electrically tested to identify known good second tier stacks and known bad second tier stacks.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chi-Hsi Wu, Wen-Chih Chiou, Hsiang-Fan Lee, Shih-Peng Tai, Tang-Jung Chiu
  • LIGHT-EMITTING DEVICE
    Publication number: 20160064632
    Abstract: A light-emitting device comprises a substrate; a plurality of light-emitting diodes formed on the substrate, wherein each of the plurality of light-emitting diodes comprises a first conductivity type layer, an active layer on the first conductivity type layer, and a second conductivity type layer on the active layer; a reflective layer surrounding a sidewall of each of the plurality of light-emitting diodes; and a top electrode formed on the reflective layer and the plurality of light-emitting diodes.
    Type: Application
    Filed: October 29, 2015
    Publication date: March 3, 2016
    Inventors: Ding-Yuan CHEN, Chia-Lin YU, Chen-Hua YU, Wen-Chih CHIOU
  • TSV Formation
    Publication number: 20160056090
    Abstract: A device includes a substrate having a front side and a backside, the backside being opposite the front side. An isolation layer is disposed on the front side of the substrate, wherein first portions of isolation layer and the substrate are in physical contact. A through substrate via (TSV) extends from the front side to the backside of the substrate. An oxide liner is on a sidewall of the TSV. The oxide liner extends between second portions of the substrate and the isolation layer. A dielectric layer having a metal pad is disposed over the isolation layer on the front side of the substrate. The metal pad and the TSV are formed of a same material.
    Type: Application
    Filed: November 5, 2015
    Publication date: February 25, 2016
    Inventors: Ku-Feng Yang, Shin-Puu Jeng, Wen-Chih Chiou