Patents by Inventor Wen-Chih Chiou

Wen-Chih Chiou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer cassette with electrostatic carrier charging scheme
    Patent number: 9570331
    Abstract: A wafer cassette includes a main body having space to hold at least one wafer assembly. Each of the at least one wafer assembly includes a wafer and an electrostatic carrier attached to the wafer. An electrical contact structure inside the main body is arranged to contact an electrical pad of the electrostatic carrier.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chih Chiou, Yung-Chi Lin, Yu-Liang Lin, Hung-Jung Tu
  • Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via and Method of Forming the Same
    Publication number: 20170011988
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 12, 2017
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Wafer Backside Interconnect Structure Connected to TSVs
    Publication number: 20170005069
    Abstract: An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 5, 2017
    Inventors: Ming-Fa Chen, Wen-Chih Chiou, Shau-Lin Shue
  • Dummy Structure for Chip-on-Wafer-on-Substrate
    Publication number: 20160358818
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • Device with capped through-substrate via structure
    Patent number: 9514986
    Abstract: A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Yen-Hung Chen, Yin-Hua Chen, Ebin Liao, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS AND METHOD OF MANUFACTURE
    Publication number: 20160329245
    Abstract: A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.
    Type: Application
    Filed: July 20, 2016
    Publication date: November 10, 2016
    Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
  • Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices
    Publication number: 20160329302
    Abstract: Packaged semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes a substrate and a plurality of integrated circuit dies coupled to the substrate. The device also includes a molding material disposed over the substrate between adjacent ones of the plurality of integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies, wherein the cap layer comprises an electrically conductive material that directly contacts the molding material and each of the plurality of integrated circuit dies.
    Type: Application
    Filed: July 18, 2016
    Publication date: November 10, 2016
    Inventors: Shin-Puu Jeng, Wen-Chih Chiou, Tu-Hao Yu, Hung-Jung Tu, Yu-Liang Lin, Shih-Hui Wang
  • Alignment mark and method of formation
    Patent number: 9478480
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Semiconductor device having backside interconnect structure through substrate via and method of forming the same
    Patent number: 9449898
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Wafer backside interconnect structure connected to TSVs
    Patent number: 9449875
    Abstract: An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Wen-Chih Chiou, Shau-Lin Shue
  • Dummy structure for chip-on-wafer-on-substrate
    Patent number: 9425126
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • Semiconductor Device and Method
    Publication number: 20160240439
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 18, 2016
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • CIS Chips and Methods for Forming the Same
    Publication number: 20160240583
    Abstract: A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Jing-Cheng Lin
  • Apparatus and method of substrate to substrate bonding for three dimensional (3D) IC interconnects
    Patent number: 9418961
    Abstract: An apparatus including a bond head, a supplemental support, a reduction module, and a transducer is provided. The bond head holds a first substrate that contains a first set of metal pads. The supplemental support holds a second substrate that contains a second set of metal pads. The aligner forms an aligned set of metal pads by aligning the first substrate to the second substrate. The reduction module contains the aligned substrates and a reduction gas flows into the reduction module. The transducer provides repeated relative motion to the aligned set of metal pads.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Through-substrate via formation with improved topography control
    Patent number: 9418933
    Abstract: A device include a substrate and an interconnect structure over the substrate. The interconnect structure comprising an inter-layer dielectric (ILD) and a first inter-metal dielectric (IMD) formed over the ILD. A through-substrate via (TSV) is formed at the IMD extending a first depth through the interconnect structure into the substrate. A metallic pad is formed at the IMD adjoining the TSV and extending a second depth into the interconnect structure, wherein the second depth is less than the first depth. Connections to the TSV are made through the metallic pad.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Semiconductor component having through-silicon vias and method of manufacture
    Patent number: 9418923
    Abstract: A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Methods of packaging semiconductor devices and packaged semiconductor devices
    Patent number: 9406650
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Wen-Chih Chiou, Tu-Hao Yu, Hung-Jung Tu, Yu-Liang Lin, Shih-Hui Wang
  • Wafer debonding and cleaning apparatus and method of use
    Patent number: 9390949
    Abstract: This description relates to a wafer debonding and cleaning apparatus including an automatic wafer handling module. The automatic wafer handling module loads a semiconductor wafer into a wafer debonding module for a debonding process. The automatic wafer handling module removes the semiconductor wafer from the debonding module and loads the semiconductor wafer into a wafer cleaning module for a cleaning process.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chih Chiou, Yu-Liang Lin, Hung-Jung Tu
  • 3D INTEGRATED CIRCUIT (3DIC) STRUCTURE AND METHOD OF MAKING SAME
    Publication number: 20160197055
    Abstract: An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 7, 2016
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Chung-Shi Liu
  • Semiconductor Device and Method
    Publication number: 20160197029
    Abstract: A semiconductor device and method are provided which utilizes a single mask to form openings for both a through substrate via as well as for a through dielectric via. In an embodiment a contact etch stop layer is deposited over and between a first semiconductor device and a second semiconductor device. A dielectric material is deposited over the contact etch stop layer between the first semiconductor device and the second semiconductor device. The different materials of the contact etch stop layer and the dielectric material is utilized such that a single mask may be used to form a through substrate via through the first semiconductor device and also to form a through dielectric via through the dielectric material.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 7, 2016
    Inventors: Cheng-Chun Tsai, Hung-Pin Chang, Ku-Feng Yang, Yi-Hsiu Chen, Wen-Chih Chiou