Patents by Inventor Wen-Ching Tsai
Wen-Ching Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128249Abstract: An electronic package is provided, in which a circuit structure is stacked on a carrier structure having a routing layer via support structures, where electronic elements are disposed on upper and lower sides of the circuit structure and the carrier structure, and the electronic elements and the support structures are encapsulated by a cladding layer, such that the electronic package can effectively increase the packaging density to meet the requirements of multi-functional end products.Type: ApplicationFiled: December 8, 2022Publication date: April 18, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chi-Ching HO
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Publication number: 20230315833Abstract: A method for managing passwords for a BIOS and a BMC is implemented by a computer including a processor, a BMC, a platform controller hub (PCH), a first non-volatile memory and a second non-volatile memory. The BMC stores a BMC password, the first non-volatile memory stores a BIOS password, and the second non-volatile memory stores a first string and a second string. The method includes steps of: upon receiving a command for changing the BIOS password, the processor changing the BIOS password via the PCH according to the command; the processor changing the second string via the PCH to be the same as the BIOS password; the processor rebooting the computer; the BMC changing the first string via the PCH to be the same as the second string; and the BMC changing the BMC password to be the same as the first string.Type: ApplicationFiled: March 8, 2023Publication date: October 5, 2023Applicant: Mitac Computing Technology CorporationInventor: Wen-Ching TSAI
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Patent number: 10971417Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.Type: GrantFiled: August 5, 2019Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
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Patent number: 10535631Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.Type: GrantFiled: December 17, 2018Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
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Publication number: 20190355640Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.Type: ApplicationFiled: August 5, 2019Publication date: November 21, 2019Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
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Patent number: 10373885Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.Type: GrantFiled: May 30, 2017Date of Patent: August 6, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
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Publication number: 20190139933Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.Type: ApplicationFiled: December 17, 2018Publication date: May 9, 2019Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
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Patent number: 10157882Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.Type: GrantFiled: September 5, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
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Publication number: 20170365579Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.Type: ApplicationFiled: September 5, 2017Publication date: December 21, 2017Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
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Publication number: 20170263519Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.Type: ApplicationFiled: May 30, 2017Publication date: September 14, 2017Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
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Patent number: 9754918Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.Type: GrantFiled: July 28, 2014Date of Patent: September 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
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Patent number: 9711379Abstract: Disclosed herein is a package comprising a first die, a second die, and an insulating film extending along sidewalls of the first die or the second die. The first die includes a first redistribution layer (RDL) disposed on a first semiconductor substrate and a conductive element in the first RDL. The second die includes a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. The package further includes a via extending from the conductive elements through the first semiconductor substrate and a spacer interposed between the first semiconductor substrate and the via. The first spacer extends from the conductive element through the first semiconductor substrate.Type: GrantFiled: April 13, 2015Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Wen-Ching Tsai, Ming-Fa Chen
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Patent number: 9698081Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.Type: GrantFiled: September 13, 2016Date of Patent: July 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
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Patent number: 9666520Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.Type: GrantFiled: August 19, 2014Date of Patent: May 30, 2017Assignee: Taiwan Semiconductor Manufactuing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
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Patent number: 9633917Abstract: Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via.Type: GrantFiled: August 20, 2015Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Ching Tsai, Ming-Fa Chen, Chen-Hua Yu
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Patent number: 9613926Abstract: Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.Type: GrantFiled: May 14, 2015Date of Patent: April 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
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Publication number: 20170053844Abstract: Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via.Type: ApplicationFiled: August 20, 2015Publication date: February 23, 2017Inventors: Wen-Ching Tsai, Ming-Fa Chen, Chen-Hua Yu
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Publication number: 20170005027Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.Type: ApplicationFiled: September 13, 2016Publication date: January 5, 2017Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
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Patent number: 9449837Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.Type: GrantFiled: March 13, 2015Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
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Publication number: 20160190089Abstract: Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.Type: ApplicationFiled: May 14, 2015Publication date: June 30, 2016Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai