Patents by Inventor Wen-Ching Tsai

Wen-Ching Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220357152
    Abstract: A material analysis method is provided. A plurality of wafers processed from a plurality of ingots are measured by a measuring instrument to obtain an average of a bow of each of the wafers processed from the ingots and a plurality of full widths at half maximum (FWHM) of each of the wafers. Key factors respectively corresponding to the ingots are calculated according to the FWHM of the wafers. A regression equation is obtained according to the key factors and the average of the bows.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 10, 2022
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Shang-Chi Wang, Wen-Ching Hsu, Chia-Chi Tsai, I-Ching Li
  • Patent number: 10971417
    Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
  • Patent number: 10535631
    Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
  • Publication number: 20190355640
    Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.
    Type: Application
    Filed: August 5, 2019
    Publication date: November 21, 2019
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
  • Patent number: 10373885
    Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: August 6, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
  • Publication number: 20190139933
    Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
  • Patent number: 10157882
    Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
  • Publication number: 20170365579
    Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
    Type: Application
    Filed: September 5, 2017
    Publication date: December 21, 2017
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
  • Publication number: 20170263519
    Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.
    Type: Application
    Filed: May 30, 2017
    Publication date: September 14, 2017
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
  • Patent number: 9754918
    Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
  • Patent number: 9711379
    Abstract: Disclosed herein is a package comprising a first die, a second die, and an insulating film extending along sidewalls of the first die or the second die. The first die includes a first redistribution layer (RDL) disposed on a first semiconductor substrate and a conductive element in the first RDL. The second die includes a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. The package further includes a via extending from the conductive elements through the first semiconductor substrate and a spacer interposed between the first semiconductor substrate and the via. The first spacer extends from the conductive element through the first semiconductor substrate.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Ching Tsai, Ming-Fa Chen
  • Patent number: 9698081
    Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
  • Patent number: 9666520
    Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufactuing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
  • Patent number: 9633917
    Abstract: Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Ching Tsai, Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 9613926
    Abstract: Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
  • Publication number: 20170053844
    Abstract: Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via.
    Type: Application
    Filed: August 20, 2015
    Publication date: February 23, 2017
    Inventors: Wen-Ching Tsai, Ming-Fa Chen, Chen-Hua Yu
  • Publication number: 20170005027
    Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.
    Type: Application
    Filed: September 13, 2016
    Publication date: January 5, 2017
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
  • Patent number: 9449837
    Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
  • Publication number: 20160190089
    Abstract: Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.
    Type: Application
    Filed: May 14, 2015
    Publication date: June 30, 2016
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
  • Publication number: 20150325520
    Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
    Type: Application
    Filed: July 28, 2014
    Publication date: November 12, 2015
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh