Patents by Inventor Wen-Ching Tsai

Wen-Ching Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7732886
    Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: June 8, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Tsan-Chi Chu, Wen-Shiang Liao, Wen-Ching Tsai
  • Publication number: 20100038645
    Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.
    Type: Application
    Filed: October 21, 2009
    Publication date: February 18, 2010
    Applicant: AU OPTRONICS CORP.
    Inventors: Po-Lin Chen, Wen-Ching Tsai, Chun-Nan Lin, Kuo-Yuan Tu
  • Publication number: 20100012974
    Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.
    Type: Application
    Filed: July 15, 2008
    Publication date: January 21, 2010
    Inventors: Hung-Lin Shih, Tsan-Chi Chu, Wen-Shiang Liao, Wen-Ching Tsai
  • Patent number: 7639536
    Abstract: A storage unit of a single-conductor non-volatile memory cell is described, which includes an isolation layer in a substrate, a storage transistor and an erasing transistor. The storage transistor includes a first well of a first conductivity type in the substrate beside the isolation layer, a floating gate crossing over the isolation layer and including a first segment over the first well, and two source/drain regions of a second conductivity type in the first well beside the first segment of the floating gate. The erasing transistor includes a second well of the first conductivity type located in the substrate and separated from the first well by the isolation layer, a second segment of the floating gate over the second well, and a well pickup region of the first conductivity type in the second well beside the second segment of the floating gate.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: December 29, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Wen-Ching Tsai, Yu-Hua Huang
  • Patent number: 7625788
    Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: December 1, 2009
    Assignee: Au Optronics Corp.
    Inventors: Po-Lin Chen, Wen-Ching Tsai, Chun-Nan Lin, Kuo-Yuan Tu
  • Patent number: 7598524
    Abstract: A thin film transistor (TFT) is disclosed, and the thin film transistor comprises: a substrate, a gate electrode, a first adhesion layer, a gate insulting layer, a semiconductor layer, and a source electrode and a drain electrode. The gate electrode is formed on the substrate, and the gate electrode is made of silver. The first adhesion layer is formed between the substrate and the gate electrode. A gate insulating layer is formed on the gate electrode. The semiconductor layer is formed on the gate insulating layer. The source electrode and the drain electrode are formed on parts of the semiconductor layer. Accordingly, the reliable TFT is provided through having the Ag metal with low resistivity and good adhesion characteristics.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: October 6, 2009
    Assignee: Au Optronics Corporation
    Inventors: Wen-Ching Tsai, Kuo-Lung Fang, Han-Tu Lin, Chia-Sheng Lee
  • Publication number: 20090225601
    Abstract: A storage unit of a single-conductor non-volatile memory cell is described, which includes an isolation layer in a substrate, a storage transistor and an erasing transistor. The storage transistor includes a first well of a first conductivity type in the substrate beside the isolation layer, a floating gate crossing over the isolation layer and including a first segment over the first well, and two source/drain regions of a second conductivity type in the first well beside the first segment of the floating gate. The erasing transistor includes a second well of the first conductivity type located in the substrate and separated from the first well by the isolation layer, a second segment of the floating gate over the second well, and a well pickup region of the first conductivity type in the second well beside the second segment of the floating gate.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 10, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Lin Shih, Wen-Ching Tsai, Yu-Hua Huang
  • Publication number: 20090206384
    Abstract: An illuminating efficiency-increasable and light-erasable memory including a substrate, a memory device, many dielectric layers, and many cap layers is provided. The substrate includes a memory region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on the substrate in the memory region. The dielectric layers are disposed on the substrate and cover the memory device. The dielectric layers have an opening located above the floating gate. Each of the cap layers is disposed on each of the dielectric layers, respectively.
    Type: Application
    Filed: April 28, 2009
    Publication date: August 20, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Lin Shih, Wen-Ching Tsai, Yu-Hua Huang
  • Publication number: 20090173944
    Abstract: A thin film transistor (TFT) includes a substrate, a gate, a gate dielectric layer, a channel layer, a source and a drain. The gate and the gate dielectric layer are disposed on the substrate and the gate dielectric layer covers the gate. The channel layer is disposed on the gate dielectric layer over the gate, and the source and the drain are respectively disposed on a portion of the channel layer at both sides of the gate. At least one of the gate, the source and the drain has a lower conductive layer, an upper conductive layer and an intermediate conductive layer located between the lower conductive layer and the upper conductive layer. The material of the lower conductive layer is different from the material of the intermediate conductive layer, and the thickness of the lower conductive layer is less than or equal to about 150 ?.
    Type: Application
    Filed: March 16, 2008
    Publication date: July 9, 2009
    Applicant: Au Optronics Corporation
    Inventors: Po-Lin Chen, Ting Hsieh, Chun-Nan Lin, Wen-Ching Tsai
  • Publication number: 20090153056
    Abstract: A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.
    Type: Application
    Filed: April 2, 2008
    Publication date: June 18, 2009
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Po-Lin Chen, Chun-Nan Lin, Shu-Feng Wu, Wen-Ching Tsai
  • Patent number: 7544992
    Abstract: An illuminating efficiency-increasable and light-erasable embedded memory structure including a substrate, a memory device, many dielectric layers, many cap layers and at least three metal layers is described. The substrate includes a memory region and a core circuit region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on the substrate in the memory region. The dielectric layers are disposed on the substrate and cover the memory device. The dielectric layers have a first opening located above the floating gate. Each of the cap layers is disposed on each of the dielectric layers, respectively. The metal layers are disposed in the dielectric layers in the core circuit region.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: June 9, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Wen-Ching Tsai, Yu-Hua Huang
  • Publication number: 20090142923
    Abstract: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).
    Type: Application
    Filed: February 6, 2009
    Publication date: June 4, 2009
    Applicant: AU OPTRONICS CORP.
    Inventors: Yu-Wei Liu, Wen-Ching Tsai, Kuo-Yu Huang, Hui-Fen Lin
  • Patent number: 7528466
    Abstract: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: May 5, 2009
    Assignee: AU Optronics Corp.
    Inventors: Yu-Wei Liu, Wen-Ching Tsai, Kuo-Yu Huang, Hui-Fen Lin
  • Publication number: 20090101903
    Abstract: A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.
    Type: Application
    Filed: August 5, 2008
    Publication date: April 23, 2009
    Inventors: Po-Lin Chen, Kuo-Yuan Tu, Wen-Ching Tsai, Chun-Nan Lin, Shu-Feng Wu
  • Publication number: 20090057668
    Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.
    Type: Application
    Filed: May 6, 2008
    Publication date: March 5, 2009
    Applicant: AU Optronics corp.
    Inventors: Po-Lin Chen, Wen-Ching Tsai, Chun-Nan Lin, Kuo-Yuan Tu
  • Publication number: 20080283893
    Abstract: An illuminating efficiency-increasable and light-erasable embedded memory structure including a substrate, a memory device, many dielectric layers, many cap layers and at least three metal layers is described. The substrate includes a memory region and a core circuit region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on the substrate in the memory region. The dielectric layers are disposed on the substrate and cover the memory device. The dielectric layers have a first opening located above the floating gate. Each of the cap layers is disposed on each of the dielectric layers, respectively. The metal layers are disposed in the dielectric layers in the core circuit region.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 20, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Lin Shih, Wen-Ching Tsai, Yu-Hua Huang
  • Publication number: 20080268586
    Abstract: The invention discloses a switching element of a pixel electrode for a display device and methods for fabricating the same. A gate is formed on a substrate. A first copper silicide layer is formed on the gate. An insulating layer is formed on the first copper silicide layer. A semiconductor layer is formed on the insulating layer. A source and a drain are formed on the semiconductor layer. Moreover, a second copper silicide layer is sandwiched between the semiconductor layer and the source/drain.
    Type: Application
    Filed: July 10, 2008
    Publication date: October 30, 2008
    Applicant: AU OPTRONICS CORP.
    Inventors: Kuo-Lung FANG, Wen-Ching TSAI, Yeong-Shyang LEE, Han-Tu LIN
  • Patent number: 7417254
    Abstract: The invention discloses a switching devise for a pixel electrode of display devise and methods for fabricating the same. A gate is formed on a portion of a substrate. A semiconductor layer is formed on the gate. A source and a drain are formed on a portion of the semiconductor layer. A low-k (low dielectric constant) materia layer, such as a layer of a-SiC:H or a-SiCN:H, is formed between the gate and the semiconductor layer and/or on the source/ drain.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: August 26, 2008
    Assignee: AU Optronics Corp.
    Inventors: Kuo-Lung Fang, Wen-Ching Tsai, Han-Tu Lin
  • Patent number: 7411212
    Abstract: The invention discloses a switching element of a pixel electrode for a display device and methods for fabricating the same. A gate is formed on a substrate. A first copper silicide layer is formed on the gate. An insulating layer is formed on the first copper silicide layer. A semiconductor layer is formed on the insulating layer. A source and a drain are formed on the semiconductor layer. Moreover, a second copper silicide layer is sandwiched between the semiconductor layer and the source/drain.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: August 12, 2008
    Assignee: AU Optronics Corp.
    Inventors: Kuo-Lung Fang, Wen-Ching Tsai, Yeong-Shyang Lee, Han-Tu Lin
  • Patent number: 7384831
    Abstract: A thin film transistor (TFT) and the manufacturing method thereof are disclosed, and the thin film transistor comprises: a substrate, a gate electrode, a first CuSix layer, a gate-insulting layer, a semiconductor layer, a second CuSix layer, and a source electrode and a drain electrode. The gate electrode is disposed on the substrate, wherein the gate electrode includes the material of copper (Cu). The first CuSix layer is disposed between the gate electrode and the substrate. The gate insulating layer is disposed on the gate electrode. The semiconductor layer is disposed on the gate insulating layer. The second CuSix layer is disposed between the source electrode and the semiconductor layer and is disposed between the drain electrode and the semiconductor layer, wherein the source electrode and the drain electrode include the material of copper (Cu). The source electrode and the drain electrode are disposed on the second CuSix layer.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: June 10, 2008
    Assignee: Au Optronics Corporation
    Inventors: Wen-Ching Tsai, Yeong-Shyang Lee, Kuo-Yuan Tu, Han-Tu Lin