Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.

Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode via and a bottom electrode over a top of the bottom electrode via. A data storage layer is over the bottom electrode and a top electrode is over the data storage layer. A top electrode via is on an upper surface of the top electrode and is centered along a first line that is laterally offset from a second line centered upon a bottommost surface of the bottom electrode via. The first line is perpendicular to the upper surface of the top electrode and parallel to the second line.

Abstract: A storage device includes: a plurality of first magnetic tunnel junction (MTJ) cells disposed on a first portion of a substrate; and a plurality of second MTJ cells disposed on a second portion different from the first portion of the substrate; wherein each of the plurality of first MTJ cells has a first cross-sectional surface area viewing from a top of the substrate, each of the plurality of second MTJ cells has a second cross-sectional surface area viewing from the top of the substrate, and the second cross-sectional surface area is greater than the first cross-sectional surface area.

Abstract: Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction.

Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.

Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.

Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.

Abstract: Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via is disposed over the top electrode. The via makes electrical contact with only a tapered sidewall of the recess without contacting a bottom surface of the recess.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode via and a bottom electrode over a top of the bottom electrode via. A data storage layer is over the bottom electrode and a top electrode is over the data storage layer. A top electrode via is on an upper surface of the top electrode and is centered along a first line that is laterally offset from a second line centered upon a bottommost surface of the bottom electrode via. The first line is perpendicular to the upper surface of the top electrode and parallel to the second line.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device has a bottom electrode arranged over a bottom electrode via. A variable resistive dielectric layer is arranged over the bottom electrode. The variable resistive dielectric layer extends to within a recess in an upper surface of the bottom electrode. A top electrode is disposed over the variable resistive dielectric layer. A top electrode via extends outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the recess within the upper surface of the bottom electrode. The top electrode via has a smaller total width than the top electrode.

Abstract: Integrated circuit structures and methods for forming the same are provided. An integrated circuit includes a dielectric layer in a memory region and a logic region. The integrated circuit structure also includes a first conductive feature in the dielectric layer in the memory region. The integrated circuit structure further includes a second conductive feature in the dielectric layer in the logic region. In addition, the integrated circuit structure includes an active memory cell over the dielectric layer in the memory region. The active memory cell is connected to the first conductive feature. The integrated circuit structure also includes a dummy memory cell over the dielectric layer in the logic region. The dummy memory cell is connected to the second conductive feature.

Abstract: The present disclosure relates to a method for determining a characteristic of a monitored layer of an integrated chip structure. In some embodiments, the method may be performed by forming an integrated chip structure over a substrate. The method further includes forming a monitor layer over the integrated chip structure. The monitor layer includes a plurality of monitor pads. The method also includes measuring an electrical property between a set of monitor pads of the plurality of monitor pads. The set of monitor pads are laterally spaced apart by a monitor pad distance. A characteristic of a region of the integrated chip structure underlying the monitor pad distance between the set of monitor pads is determined based on the measured electrical property.

Abstract: A method of forming a magnetoresistive random access memory (MRAM) device including a perpendicular MTJ (magnetic tunnel junction) is provided. The method includes forming a magnetic tunneling junction (MTJ) over a bottom electrode layer. A top electrode layer is formed over an upper surface of the MTJ, and a hard mask is formed over an upper surface of the top electrode layer. A first etch is performed through the top electrode layer, through regions of the MTJ unmasked by the hard mask, to form a top electrode and an etched MTJ. Sidewall spacers are formed extending from an upper surface of the hard mask or the top electrode, along sidewalls of the top electrode and the etched MTJ, to a point below or about even with an upper surface of the bottom electrode. A resulting MRAM device structure is also provided.