Patents by Inventor Wen-Chun YOU

Wen-Chun YOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9172036
    Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: October 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao, Wen-Chun You, Sheng-Hung Shih
  • Patent number: 9112148
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You
  • Patent number: 9076522
    Abstract: A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: July 7, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chun You, Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Yu-Wen Liao, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Ting Chu
  • Publication number: 20150144859
    Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao, Wen-Chun You, Sheng-Hung Shih
  • Publication number: 20150092471
    Abstract: A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chun YOU, Kuo-Chi TU, Chih-Yang CHANG, Hsia-Wei CHEN, Yu-Wen LIAO, Chin-Chieh YANG, Sheng-Hung SHIH, Wen-Ting CHU
  • Publication number: 20150090949
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsai-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You
  • Publication number: 20150069315
    Abstract: One embodiment in the present disclosure provides a resistor in a resistive random access memory (RRAM). The resistor includes a first electrode; a resistive layer on the first electrode; an electric field enhancement array in the resistive layer; and a second electrode on the resistive layer. The electric field enhancement array includes a plurality of electric field enhancers arranged in a same plane. One embodiment in the present disclosure provides a method of manufacturing a resistor structure in an RRAM. The method comprises (1) forming a first resistive layer on a first electrode; (2) forming a metal layer on the resistive layer; (3) patterning the metal layer to form a metal dot array on the resistive layer; and (4) forming a second electrode on the metal dot array. The metal dot array comprises a plurality of metal dots, and a distance between adjacent metal dots is less than 40 nm.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: SHENG-HUNG SHIH, WEN-TING CHU, KUO-CHI TU, YU-WEN LIAO, CHIH-YANG CHANG, CHIN-CHIEH YANG, HSIA-WEI CHEN, WEN-CHUN YOU, CHIH-MING CHEN
  • Publication number: 20140264233
    Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround at least the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.
    Type: Application
    Filed: May 16, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi TU, Chih-Yang CHANG, Hsia-Wei CHEN, Yu-Wen LIAO, Chin-Chieh YANG, Wen-Chun YOU, Sheng-Hung SHIH, Wen-Ting CHU