Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Abstract: Chimeric antigen receptors targeted to IL-13Ra2 are described. The targeting domain is a IL13 variant having increased specificity for IL-13Ra2 relative to IL-13Ra1.

Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substrate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substrate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

Abstract: A method for automatically generating news event of a certain topic applied in an electronic device analyzes text of the news event by a topic model to obtain topics, a probability distribution of keywords in each topic is established, and a time interval distribution of the keywords in each topic is calculated. Keywords within a preset probability distribution range are selected to reduce the size of a word bag relating to the topic, and a time interval range of the reduced word bag of the topic is determined. A calculation of text similarities of the text in a database is made to obtain a news article corresponding to each topic according to the time interval range of the reduced word bag, and a title of the news article as a target topic of the text of the news event is determined.

Abstract: An external control device for a game controller is provided, including a casing, a second adapter, a mode selector, a memory, and a conversion circuit. The second adapter is provided for being connected to the first adapter of the game controller. The mode selector is provided for outputting one of selection signals. The memory stores different encode data. The conversion circuit selects encode data according to the selection signals output from the mode selector, and encodes and converts the button signal into a pre-formatted wireless signal according to the selected encode data, and then sends the pre-formatted wireless signal through a wireless signal transmitting circuit. Thus, the button signal of the game controller is converted into a wireless signal corresponding to another game console providing another game control device integrating the game controller with the external control device, which has the same effect.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

Abstract: An external control device for a game controller is provided, including a casing, a second adapter, a mode selector, a memory, and a conversion circuit. The second adapter is provided for being connected to the first adapter of the game controller. The mode selector is provided for outputting one of selection signals. The memory stores different encode data. The conversion circuit selects encode data according to the selection signals output from the mode selector, and encodes and converts the button signal into a pre-formatted wireless signal according to the selected encode data, and then sends the pre-formatted wireless signal through a wireless signal transmitting circuit. Thus, the button signal of the game controller is converted into a wireless signal corresponding to another game console providing another game control device integrating the game controller with the external control device, which has the same effect.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

Abstract: A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.

Abstract: The present invention provides a radiotherapy system that can monitor a target location in real time. The radiotherapy system includes a remote control system operable to actuate a real-time image capturing device to acquire images in real time for monitoring the target location. The system also includes an image registration system that can register the acquired image with an image previously captured for the treatment plan, whereby it can be determined whether the patient's tumor is in the beam's eye view of the treatment plan. By confirming that the tumor is in the range of the beam's eye view, the accuracy of the treatment can be improved, and the irradiated area can be reduced, which makes the radiation treatment safer.

Abstract: A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.

Abstract: A method for manufacturing a non-volatile memory with SONOS memory cells, which includes steps of: providing a substrate; forming a first gate oxide layer and a first gate conductive layer onto the substrate; forming a MOS transistor gate by executing a photolithography process on the first gate conductive layer, and then forming an ONO structure on the substrate; and forming a second gate conductive layer on the ONO substrate, and then forming a NVM transistor gate by executing a photolithography process on the second gate conductive layer.

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.

Abstract: A method for manufacturing a non-volatile memory with SONOS memory cells, which includes steps of: providing a substrate; forming a first gate oxide layer and a first gate conductive layer onto the substrate; forming a MOS transistor gate by executing a photolithography process on the first gate conductive layer, and then forming an ONO structure on the substrate; and forming a second gate conductive layer on the ONO substrate, and then forming a NVM transistor gate by executing a photolithography process on the second gate conductive layer.

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.