Abstract: A semiconductor cell structure includes a first complementary metal oxide silicon (CMOS) a second CMOS, a first conducting element, and a second conducting element. The first and second CMOSs are disposed on the substrate and a reference voltage is provided to the first CMOS and the second CMOS respectively through the first conducting element and the second conducting element. A product of a width of the first conducting element multiplied by a channel length of the first CMOS is positively related to a product of a width of the second conducting element multiplied by a channel length of the second CMOS.

Abstract: An antenna element comprises one or more directors, a resonator, and a three dimensional ground assembly. Parts of the antenna element are arranged on three metal layers. A top layer has an unconnected metal bar which forms a beam director, a resonator and a top part of the ground assembly. The resonator is an integral piece substantially in the form of a loop connected to a feed line and a feed line terminal ending. The feed line terminal ending serves as the ground plane for the feed line as well as providing impedance matching from the external transceiver circuit to the resonator. The ground assembly includes a top layer ground connected to a plurality of metallized half cylindrical hole channels (or metallized via holes) which connect to a ground terminal in a bottom layer.

Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

Abstract: Methods and apparatus for forming reflector films are described A liner is formed on a substrate surface followed by formation of the reflector layer so that there is no oxygen exposure between liner and reflector layer formation. In some embodiments, a high aspect ratio structure is filled with a reflector material by partially filling the structure with the reflector material while growth is inhibited at a top portion of the structure, reactivating the top portion of the substrate and then filling the structure with the reflector material.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.

Abstract: The present invention relates to an isolated strain of lactic acid bacteria (LAB) for inhibiting drug-resistant Enterobacteriaceae, in which the isolated strain of the LAB includes Lacticaseibacillus rhamnosus JJ101, Lacticaseibacillus paracasei JJ102 and/or Lactiplantibacillus plantarum JJ103, and the isolated strain of the LAB inhibit growth of the drug-resistant Enterobacteriaceae. After orally administered to a subject, the isolated strain of the LAB can inhibit the growth of the drug-resistant Enterobacteriaceae, and thus can potentially be used to prevent, improve and/or treat the infection of the drug-resistant Enterobacteriaceae.

Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

Abstract: A manufacturing method of a metal bump structure is provided. A driving base is provided. At least one pad and an insulating layer are formed on the driving base. The pad is formed on an arrangement surface of the driving base and has an upper surface. The insulating layer covers the arrangement surface of the driving base and the pad, and exposes a part of the upper surface of the pad. A patterned metal layer is formed on the upper surface of the pad exposed by the insulating layer, and extends to cover a part of the insulating layer. An electro-less plating process is performed to form at least one metal bump on the patterned metal layer. A first extension direction of the metal bump is perpendicular to a second extension direction of the driving base.

Abstract: The present disclosure relates to an electronic load apparatus. An embodiment of the present disclosure includes an electronic load apparatus including: a measurement resistor, a reference circuit, a transistor, and a feedback circuit. The measurement resistor includes a first contact, a second contact, a third contact, and a fourth contact. The first contact and the second contact are located at a first end of the measurement resistor. The third contact and the fourth contact are located at a second end of the measurement resistor. A reference power (or a reference voltage) electrically connects to the reference circuit. The reference circuit and the first contact of the measurement resistor are electrically connected. The transistor includes a drain, a gate, and a source. The reference circuit and the gate of the transistor are electrically connected. One of the source and the drain of the transistor electrically connects to the second contact of the measurement resistor.

Abstract: A display device with sensing element includes a substrate having a disposing surface, a plurality of display elements, at least one sensing element, and at least one lighting adjustment element. The display elements are disposed above the disposing surface to present an image. The at least one sensing element disposed above the disposing surface to sense a light brightness projected toward either side of the substrate. The at least one light adjustment element is in signal transmittable connection with the display elements and the at least one sensing element. The at least one light adjustment element adjusts a plurality of control signals inputted into the display elements to determine a contrast of the image.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.

Abstract: The present disclosure provides a biomaterial and a method for promoting tissue regeneration by using the biomaterial.

Abstract: A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.

Abstract: A method for detecting defects in a GaN high electron mobility transistor is disclosed. The method includes steps of measuring a plurality of electrical characteristics of a GaN high electron mobility transistor, measuring the plurality of electrical characteristics after performing a deterioration test on the GaN high electron mobility transistor, irradiating the GaN high electron mobility transistor in turns with a plurality of light sources with different wavelengths and measuring the plurality of electrical characteristics after each irradiation of the GaN high electron mobility transistor by each of the plurality of light sources, and comparing changes of the plurality of electrical characteristics measured in the above steps to determine the defect location of the GaN high electron mobility transistor.

Abstract: A method for drying a wafer at room temperature includes a cleaning step, a reacting step and a pressure releasing step. The cleaning step includes putting a processing workpiece into a cleaning solvent. The reacting step includes putting the processing workpiece along with the cleaning solvent into a reaction chamber, implanting a supercritical fluid into the reaction chamber, and increasing a pressure of the reaction chamber to dissolve the cleaning solvent in the supercritical fluid. A critical temperature of the supercritical fluid is below room temperature. The pressure releasing step includes releasing the pressure of the reaction chamber and discharging the supercritical fluid together with the cleaning solvent out of the reaction chamber, after completely dissolving the cleaning solvent in the supercritical fluid.

Abstract: The present disclosure relates to an electronic load apparatus. An embodiment of the present disclosure includes an electronic load apparatus including: a measurement resistor, a reference circuit, a transistor, and a feedback circuit. The measurement resistor includes a first contact, a second contact, a third contact, and a fourth contact. The first contact and the second contact are located at a first end of the measurement resistor. The third contact and the fourth contact are located at a second end of the measurement resistor. A reference power (or a reference voltage) electrically connects to the reference circuit. The reference circuit and the first contact of the measurement resistor are electrically connected. The transistor includes a drain, a gate, and a source. The reference circuit and the gate of the transistor are electrically connected. One of the source and the drain of the transistor electrically connects to the second contact of the measurement resistor.

Abstract: A p-GaN high electron mobility transistor is disclosed. The p-GaN high electron mobility transistor includes a substrate, a channel layer located on the substrate, a supply layer laminated on the channel layer, and a doped layer laminated on the supply layer. A doping concentration of the doped layer is gradually distributed, in which the doping concentration in a first doped region close to the supply layer is lower than a doping concentration in a second doped region distant from the supply layer. A gate electrode is located on the doped layer. A source electrode and a drain electrode are respectively electrically connected to the channel layer and the supply layer.

Abstract: A GaN high electron mobility transistor is disclosed. The GaN high electron mobility transistor includes a substrate, a buffer layer located on the substrate, a barrier layer laminated on the buffer layer, a channel layer laminated on the barrier layer, a supply layer laminated on the channel layer. The barrier layer has either a p-type semiconductor or a wide band gap material. A gate electrode is located on the supply layer. A source electrode and a drain electrode are electrically connected to the channel layer and the supply layer.

Abstract: A structure to increase the breakdown voltage of the high electron mobility transistor is provided to solve the problem of function loss under a high voltage state. The structure includes a substrate, a conducting layer located on the substrate, a gate insulating layer and an electric-field-dispersion layer. The upper portion of the conducting layer is an electron supply layer, and the lower portion of the conducting layer is an electron tunnel layer. The gate insulating layer is laminated on the electron supply layer. The electric-field-dispersion layer is laminated on the gate insulating layer. The dielectric constant of the electric-field-dispersion layer is smaller than that of the gate insulating layer. A gate electrode is located between the electric-field-dispersion layer and the gate insulating layer. A source and a drain electrodes are respectively electrically connected to the electric-field-dispersion layer, the gate insulating layer, the electron supply layer, and the electron tunnel layer.