Abstract: The device for simulating a rectified constant impedance load provide by the present invention is to test a power product and comprises an analog-digital converter, a digital signal processor, a digital-analog converter, and an active electrical load module in order to replacing the passive components of a traditional rectified passive load.

Abstract: According to an apparatus and method for detecting an obstacle through stereovision, an image capturing module comprises a plurality of cameras and is used for capturing a plurality of images; an image processing module edge-detecting the image to generate a plurality of edge objects and object information corresponding to each edge object; an object detection module matches a focus and a horizontal spacing interval of the camera according to the object information to generate a relative object distance corresponding to each edge object; a group module compares the relative object distance with a threshold distance and groups the edge objects with the relative object distance smaller than the threshold distance to be an obstacle and obtains a relative obstacle distance corresponding to the obstacle.

Abstract: The present disclosure provides for processing units, which are capable of concurrently executing instructions, and a source arbitrator. The source arbitrator determines whether instructions for the processing units are read from different sources. If the source arbitrator determines that each processing unit reads its respective instruction from a different source, then the instructions from the various sources are provided to their corresponding processing units for substantially concurrent processing.

Abstract: The present disclosure provides system and method embodiments for synchronizing access to memory between a plurality of modules in a pipelined system. One system embodiment, among others, includes an upstream module and a downstream module that each share one or more locations in memory. The upstream module is configured to receive a command pair having matched identifiers, one half (wait command) of which enables the upstream module to delay access to the memory to avoid read-after-write (RAW) hazard, the other half (signal command) which is passed to the downstream module. The downstream module passes the identifier from the signal command to the upstream module at a time corresponding to the downstream module reaching an idle state, thus ceasing access to the memory. The upstream module, upon determining that the identifier received over a direct connection from the downstream module is from the command pair, accesses the one or more locations in the memory.

Abstract: A system and method for supporting multiple graphics processing units (GPUs) includes a first communication path coupled to a root complex device and a first connection point of a first GPU. A second communication path is coupled to the root complex device and a first set of switches. The first set of switches is configured to route communications between the root complex device to either a second connection point of the first GPU via a second set of switches or to a first connection point of a second GPU. The second set of switches is coupled to a second connection point of the first GPU. The second set of switches is configured to route communications to and from the second connection point of the first GPU and to either the root complex device via the first set of switches or to a second connection point of the second GPU.

Abstract: Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.

Abstract: The present disclosure provides system and method embodiments for synchronizing access to memory between a plurality of modules in a pipelined system. One system embodiment, among others, includes an upstream module and a downstream module that each share one or more locations in memory. The upstream module is configured to receive a command pair having matched identifiers, one half (wait command) of which enables the upstream module to delay access to the memory to avoid read-after-write (RAW) hazard, the other half (signal command) which is passed to the downstream module. The downstream module passes the identifier from the signal command to the upstream module at a time corresponding to the downstream module reaching an idle state, thus ceasing access to the memory. The upstream module, upon determining that the identifier received over a direct connection from the downstream module is from the command pair, accesses the one or more locations in the memory.

Abstract: The computer graphics system is configured to improve the performance of a stencil shadow volume method for rendering shadows. The apparatus and methods utilize a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil buffer is capable of storing stencil shadow volume data for each pixel and a compressed stencil buffer is capable of storing stencil shadow volume data for a group of pixels. The compressed stencil buffer is utilized with a compressed stencil buffer cache to perform a stencil shadow volume operation more efficiently than present methods.

Abstract: A system and method for supporting multiple graphics processing units (GPUs) includes a first communication path coupled to a root complex device and a first connection point of a first GPU. A second communication path is coupled to the root complex device and a first set of switches. The first set of switches is configured to route communications between the root complex device to either a second connection point of the first GPU via a second set of switches or to a first connection point of a second GPU. The second set of switches is coupled to a second connection point of the first GPU. The second set of switches is configured to route communications to and from the second connection point of the first GPU and to either the root complex device via the first set of switches or to a second connection point of the second GPU.

Abstract: Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.

Abstract: Multiple graphics processor system and method embodiments are disclosed. One system embodiment, among others, comprises a multiple graphics processor system, comprising a first graphics processing unit having first status information and a second graphics processing unit having second status information, and first key logic corresponding to the first graphics processing unit, the first key logic configured to compare the first and second status information and communicate to the first graphics processing unit a key corresponding to the lowest completed stage of processing among the first and second graphics processing units.

Abstract: Packet processing system and method embodiments implemented in a peripheral component interconnect-express (PCIE) compliant system are disclosed. One method embodiment, among others, comprises receiving a packet having at least a first type of data and a second type of data over a PCIE connection, and segregating the entire packet into two contiguous groups, a first group comprising the first type of data and a second group comprising the second type of data.

Abstract: The present disclosure relates to caches that are capable of improving processor performance. In some embodiments, among others, a cache request is received, and logic within the cache determines whether the received cache request results in a hit on the cache. If the cache request results in a hit on the cache, then that cache request is serviced. Conversely, if the cache request does not result in a hit (e.g., miss, miss-on-miss, hit-on-miss, etc.), then information related to the received cache request is stored in a missed request table. For some embodiments, missed read requests are stored in a missed read request table, while missed write requests are stored in a missed write request table.

Abstract: The present disclosure provides for processing units, which are capable of concurrently executing instructions, and a source arbitrator. The source arbitrator determines whether instructions for the processing units are read from different sources. If the source arbitrator determines that each processing unit reads its respective instruction from a different source, then the instructions from the various sources are provided to their corresponding processing units for substantially concurrent processing.

Abstract: A treadmill includes a treadbelt disposed in a deck, a motor coupled to drive the treadbelt, an incline controller to selectively adjust the deck to different inclinations, a driver coupled to a microprocessor unit and the motor and the incline controller, to control the motor and the incline controller to adjust the treadbelt to different driving speeds and to adjust the deck to different inclinations. A sensor is coupled to the microprocessor unit, to detect rotational speed of the treadbelt. The driver actuates the motor to increase or to decrease the driving speed of the treadbelt when detected driving speed of the treadbelt is greater or lower than the predetermined average speed of the treadbelt.

Abstract: The computer graphics system is configured to generate a shadow effect with a stencil shadow volume method using a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil buffer is capable of storing stencil shadow volume data for each pixel and a compressed stencil buffer is capable of storing stencil shadow volume data for a group of pixels.

Abstract: The computer graphics system is configured to improve the performance of a stencil shadow volume method for rendering shadows. The apparatus and methods utilize a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil buffer is capable of storing stencil shadow volume data for each pixel and a compressed stencil buffer is capable of storing stencil shadow volume data for a group of pixels. The compressed stencil buffer is utilized with a compressed stencil buffer cache to perform a stencil shadow volume operation more efficiently than present methods.

Abstract: The computer graphics system is configured to generate a shadow effect with a stencil shadow volume method using a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil buffer is capable of storing stencil shadow volume data for each pixel and a compressed stencil buffer is capable of storing stencil shadow volume data for a group of pixels.

Abstract: An inkjet pen including an ink reservoir for storing ink and providing ink for jetting. A port, located on top of the ink reservoir, fluid-communicated with the ambient air, is used for adjusting the air pressure inside the reservoir. A valve, operated by a spring or a resilient element, normally seals the port, while occasionally opening the port to introduce air into the reservoir when the ink level is low and the underpressure rises. In other embodiments, an elastic bag is included in the reservoir that has an opening communicated with the ambient air through a second port formed on top of the reservoir. The elastic bag expands in response to the increasing underpressure generated in the reservoir when ink is being used. The bag expansion actuates the opening of the valve so as to regulate the underpressure.

Abstract: An air pressure regulating device for ink cartridges that is not affected or interfered with by magnetic fields. In accordance with the invention a ventilating vent is settled inside the ink cartridge so that the inside region of the ink cartridge is open to the ambient air and at the same time this ventilating vent is also directed to a fixed seat. In the fixed seat a gas vent is settled to direct to the ink cartridge. On the outside region of the gas vent settled in the fixed seat a layer of elastic gastight material is covered such that it can be utilized to seal the gas vent to keep the ink cartridge sealed under ordinary conditions. When the pressure difference between the outside and inside regions of the ink cartridge reaches a critical value, the layer of the elastic gastight material is slightly pushed away so that a small quantity of air can flow into the ink cartridge to return the pressure to within a normal operating range.