Abstract: An identity recognition system includes a target region acquisition module, a photoplethysmography signal conversion module, a biometric characteristic conversion module, a face characteristic acquisition module, and a comparison module. The target region acquisition module is configured to acquire a plurality of target region images from a plurality of face images. The photoplethysmography signal conversion module is configured to generate a photoplethysmography signal according to the target region images. The biometric characteristic conversion module is configured to convert the photoplethysmography signal into a biometric characteristic. The face characteristic acquisition module is configured to acquire a face characteristic from the face images.

Abstract: Herein disclosed is a resistor comprising a resistance bar and a plurality of dividing connectors. The resistance bar has a first end and a second end and provides a first current path, which stretches from the first end to the second end along the resistance bar. The distance between the first end and the second end is less than the length of the first current path. The first and second ends are configured to be electrically connected to a power source. The dividing connectors are electrically connected to different locations on the first current path. Each of the dividing connectors has a contact pad. The resistance bar is not coplanar with the contact pads. A divided voltage is obtained from a pair of dividing connectors chosen from the plurality of dividing connectors.

Abstract: A method for bonding a first component to a second component includes placing the first and second components in a cavity. Each of the first and second components has a bonding portion, and the bonding portion of the first component faces the bonding portion of the second component. A supercritical fluid is then introduced into the cavity with a temperature of 40-400° C. and a pressure of 1,500-100,000 psi, and a pressure of 4-100,000 psi is applied on both the first and second components, assuring the bonding portion of the first component bond to the bonding portion of the second component. Moreover, a method for separating a first component from a second component includes placing a composite in a cavity. The composite includes the first component, the second component and a connecting layer by which the first component joins to the second component. The supercritical is then introduced into the cavity.

Abstract: A multi-level DC-DC converter device includes an inverter, a 3-winding high-frequency transformer, a first full-bridge rectifier, a second full-bridge rectifier, a selective circuit and a filter circuit. A first winding at a primary side of the high-frequency transformer connects with the inverter while a second winding and a third winding of at a secondary side of the high-frequency transformer connect with the first full-bridge rectifier and the second full-bridge rectifier. The selective circuit connects with DC output ports of the first full-bridge rectifier and the second full-bridge rectifier, thereby operationally selecting two serially-connected full-bridge rectifiers or single full-bridge rectifier to output two voltage levels performed as a multi-level output voltage. The filter circuit connects between the selective circuit and a load for filtering harmonics and outputting a DC voltage.

Abstract: A DC-DC converter is operated in a boost mode by operating a plurality of low-voltage side switches with a first fixed duty cycle (greater than 0.5), with cutting off a plurality of the first high-voltage side switches and a plurality of the second high-voltage side switches, with conducting a plurality of the first diodes of the first high-voltage side switches and a plurality of the second diodes of the second high-voltage side switches, and with alternatively conducting and cutting off a bidirectional switch. In a buck mode, the low-voltage side switches are cut off and a plurality of diodes of the low-voltage side switches are conducted. Furthermore, the first high-voltage side switches are complemented and are operated with a second fixed duty cycle (less than 0.5) while the second high-voltage side switches are conducted and cut off alternatively and the bidirectional switch is switched on and off.

Abstract: A DC-DC converter is operated in a boost mode by operating a plurality of low-voltage side switches with a first fixed duty cycle (greater than 0.5), with cutting off a plurality of the first high-voltage side switches and a plurality of the second high-voltage side switches, with conducting a plurality of the first diodes of the first high-voltage side switches and a plurality of the second diodes of the second high-voltage side switches, and with alternatively conducting and cutting off a bidirectional switch. In a buck mode, the low-voltage side switches are cut off and a plurality of diodes of the low-voltage side switches are conducted. Furthermore, the first high-voltage side switches are complemented and are operated with a second fixed duty cycle (less than 0.5) while the second high-voltage side switches are conducted and cut off alternatively and the bidirectional switch is switched on and off.

Abstract: A multi-level DC-DC converter device includes an inverter, a 3-winding high-frequency transformer, a first full-bridge rectifier, a second full-bridge rectifier, a selective circuit and a filter circuit. A first winding at a primary side of the high-frequency transformer connects with the inverter while a second winding and a third winding of at a secondary side of the high-frequency transformer connect with the first full-bridge rectifier and the second full-bridge rectifier. The selective circuit connects with DC output ports of the first full-bridge rectifier and the second full-bridge rectifier, thereby operationally selecting two serially-connected full-bridge rectifiers or single full-bridge rectifier to output two voltage levels performed as a multi-level output voltage. The filter circuit connects between the selective circuit and a load for filtering harmonics and outputting a DC voltage.

Abstract: A high voltage (HV) semiconductor device includes: a semiconductor substrate having a first conductivity type; a gate structure disposed over a portion of the semiconductor substrate; a pair of spacers respectively disposed over a sidewall of the gate structure, wherein one of the spacers is a composite spacer comprising a first insulating spacer contacting the gate structure, a dummy gate structure, and a second insulating spacer; a first drift region disposed in a portion of the semiconductor, underlying a portion of the gate structure and one of the pair of spacers, having a second conductivity type opposite to the first conductivity type; and a pair of doping regions, respectively disposed in a portion of the semiconductor substrate on opposite sides of the gate structure, wherein the pair of doping regions include the second conductivity type and one of the doping regions is disposed in the first drift region.

Abstract: The invention discloses the asynchronous photography for dual camera apparatus and processing the method for real-time forward vehicle detection. Image is captured by a pair of monochrome camera and stored into a computer. After the video pre-process, the edge information is used to locate the forward vehicle position, and then obtained the disparity from a fast comparison search algorithm by the stereo vision methodology. Proposed algorithm calculation of the invention can conquer the asynchronous exposure problem from dual camera and lower the hardware cost.

Abstract: The device for simulating a rectified constant impedance load provide by the present invention is to test a power product and comprises an analog-digital converter, a digital signal processor, a digital-analog converter, and an active electrical load module in order to replacing the passive components of a traditional rectified passive load.

Abstract: According to an apparatus and method for detecting an obstacle through stereovision, an image capturing module comprises a plurality of cameras and is used for capturing a plurality of images; an image processing module edge-detecting the image to generate a plurality of edge objects and object information corresponding to each edge object; an object detection module matches a focus and a horizontal spacing interval of the camera according to the object information to generate a relative object distance corresponding to each edge object; a group module compares the relative object distance with a threshold distance and groups the edge objects with the relative object distance smaller than the threshold distance to be an obstacle and obtains a relative obstacle distance corresponding to the obstacle.

Abstract: Multiple graphics processor system and method embodiments are disclosed. One system embodiment, among others, comprises a multiple graphics processor system, comprising a first graphics processing unit having first status information and a second graphics processing unit having second status information, and first key logic corresponding to the first graphics processing unit, the first key logic configured to compare the first and second status information and communicate to the first graphics processing unit a key corresponding to the lowest completed stage of processing among the first and second graphics processing units.

Abstract: An electronic load device provided for testing an OT (power supply to be tested) and the working bandwidth is regulated and set according to the output impedance of the OT. The electronic load device comprises a CPU, an impedance-bandwidth table, a voltage-current measurement unit, a power stage and a control module. Firstly, a current pulled out from the OT to the power stage is called by the CPU. Thereafter, an output impedance of the OT is measured by the voltage-current measurement unit and analysis by the CPU. Next, a working bandwidth of the electronic load device is regulated and set by the control module according to the output impedance and the impedance-bandwidth table.

Abstract: An electronic load simulates an LED is to output a simulation signal after receiving an input signal. The simulation signal has a voltage value and a current value approximating to a characteristic curve of a real LED. The electronic load comprises a processor, an amplifier, and a control unit. The processor receives a control command to set up the LED. The control command includes a forward voltage parameter and an equivalent impedance parameter. The control unit generates an adjustment command according to the foregoing parameters and the voltage of the power source. The amplifier receives and further adjusts the adjustment command so as to output the simulation signal.

Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises providing a substrate with a logic device region and a memory device region. A logic device with a first silicide region and a first silicide block region and a memory device with a second silicide region and a second silicide block region are formed in the logic device region and the memory device region, respectively. A first insulating layer is formed covering the first and second silicide block regions. A silicide process is performed to form a silicide layer on the first and second silicide regions. An underlying second insulating layer and an insulating barrier layer are formed covering the first insulating layer and the silicide layer.

Abstract: Packet processing system and method embodiments implemented in a peripheral component interconnect-express (PCIE) compliant system are disclosed. One method embodiment, among others, comprises receiving a packet having at least a first type of data and a second type of data over a PCIE connection, and segregating the entire packet into two contiguous groups, a first group comprising the first type of data and a second group comprising the second type of data.

Abstract: The invention discloses the asynchronous photography for dual camera apparatus and processing the method for real-time forward vehicle detection. Image is captured by a pair of monochrome camera and stored into a computer. After the video pre-process, the edge information is used to locate the forward vehicle position, and then obtained the disparity from a fast comparison search algorithm by the stereo vision methodology. Proposed algorithm calculation of the invention can conquer the asynchronous exposure problem from dual camera and lower the hardware cost.

Abstract: A semiconductor structure and method for forming the same are provided. The semiconductor structure comprises a semiconductor substrate, a plurality of top metallizations on the semiconductor substrate, a high density plasma layer filling gaps between the top metallizations and having a substantially planar upper surface overlying the top metallizations, and a passivation layer overlying the high density plasma layer. A metal bump can be formed overlying the top metallizations through the passivation layer and HDPCVD layer for subsequent bonding.

Abstract: An electronic load device provided for testing an OT (power supply to be tested) and the working bandwidth is regulated and set according to the output impedance of the OT. The electronic load device comprises a CPU, an impedance-bandwidth table, a voltage-current measurement unit, a power stage and a control module. Firstly, a current pulled out from the OT to the power stage is called by the CPU. Thereafter, an output impedance of the OT is measured by the voltage-current measurement unit and analysis by the CPU. Next, a working bandwidth of the electronic load device is regulated and set by the control module according to the output impedance and the impedance-bandwidth table.

Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises providing a substrate with a logic device region and a memory device region. A logic device with a first silicide region and a first silicide block region and a memory device with a second silicide region and a second silicide block region are formed in the logic device region and the memory device region, respectively. A first insulating layer is formed covering the first and second silicide block regions. A silicide process is performed to form a silicide layer on the first and second silicide regions. An underlying second insulating layer and an insulating barrier layer are formed covering the first insulating layer and the silicide layer.