Patents by Inventor Wen-Hao Ching

Wen-Hao Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11164880
    Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 2, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chih-Hsin Chen, Wei-Ren Chen
  • Publication number: 20210074855
    Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 11, 2021
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
  • Publication number: 20200006508
    Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.
    Type: Application
    Filed: March 29, 2019
    Publication date: January 2, 2020
    Inventors: Chun-Yuan LO, Shih-Chen WANG, Wen-Hao CHING, Chih-Hsin CHEN, Wei-Ren CHEN
  • Patent number: 10255980
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 9, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Patent number: 10224108
    Abstract: A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 5, 2019
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wen-Hao Ching, Shih-Chen Wang
  • Patent number: 10181342
    Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: January 15, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chun-Chieh Chao
  • Publication number: 20180315462
    Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.
    Type: Application
    Filed: November 3, 2017
    Publication date: November 1, 2018
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chun-Chieh Chao
  • Publication number: 20180197872
    Abstract: A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 12, 2018
    Inventors: Wen-Hao CHING, Shih-Chen Wang
  • Publication number: 20180190357
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 5, 2018
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Patent number: 9941011
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: April 10, 2018
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Patent number: 9792993
    Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: October 17, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching
  • Publication number: 20170206969
    Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.
    Type: Application
    Filed: January 16, 2017
    Publication date: July 20, 2017
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching
  • Publication number: 20170206968
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Application
    Filed: November 16, 2016
    Publication date: July 20, 2017
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Patent number: 9666279
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Grant
    Filed: June 26, 2016
    Date of Patent: May 30, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Patent number: 9633729
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: April 25, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Publication number: 20160307629
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Application
    Filed: June 26, 2016
    Publication date: October 20, 2016
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Patent number: 9466392
    Abstract: A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: October 11, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Chen Chang, Wen-Hao Ching, Chih-Hsin Chen, Shih-Chen Wang, Ching-Sung Yang
  • Patent number: 9425204
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: August 23, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Publication number: 20160104537
    Abstract: A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.
    Type: Application
    Filed: October 13, 2015
    Publication date: April 14, 2016
    Inventors: Wei-Chen Chang, Wen-Hao Ching, Chih-Hsin Chen, Shih-Chen Wang, Ching-Sung Yang
  • Publication number: 20160035421
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Application
    Filed: October 7, 2015
    Publication date: February 4, 2016
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang