Patents by Inventor Wen-Hao Ching

Wen-Hao Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8355282
    Abstract: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: January 15, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Shih-Chen Wang, Ching-Sung Yang
  • Publication number: 20120273860
    Abstract: An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.
    Type: Application
    Filed: July 4, 2012
    Publication date: November 1, 2012
    Applicant: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang
  • Publication number: 20120236646
    Abstract: The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.
    Type: Application
    Filed: May 29, 2012
    Publication date: September 20, 2012
    Inventors: Te-Hsun Hsu, Wei-Ren Chen, Wen-Hao Ching, Wen-Chuan Chang
  • Publication number: 20120236635
    Abstract: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.
    Type: Application
    Filed: June 1, 2012
    Publication date: September 20, 2012
    Inventors: Wen-Hao Ching, Shih-Chen Wang, Ching-Sung Yang
  • Patent number: 8199578
    Abstract: A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: June 12, 2012
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Ching-Sung Yang
  • Patent number: 8089798
    Abstract: A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: January 3, 2012
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho
  • Publication number: 20110310669
    Abstract: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.
    Type: Application
    Filed: June 17, 2010
    Publication date: December 22, 2011
    Inventors: Wen-Hao Ching, Shih-Chen Wang, Ching-Sung Yang
  • Publication number: 20110299336
    Abstract: A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 8, 2011
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Ching-Sung Yang
  • Publication number: 20110242893
    Abstract: A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.
    Type: Application
    Filed: March 30, 2010
    Publication date: October 6, 2011
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang
  • Patent number: 7872898
    Abstract: A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first doped region and the second doped region are of a second conductive type which is different from the first conductive type. A third doped region of the first conductive type is disposed in the substrate and is adjacent to the second doped region, and a junction is formed between the third doped region and the second doped region. A metal silicide layer is disposed on the substrate. An clearance is formed in the metal silicide layer, and the clearance at least exposes the junction.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: January 18, 2011
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Shih-Chen Wang, Tsung-Mu Lai
  • Publication number: 20100265755
    Abstract: A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first doped region and the second doped region are of a second conductive type which is different from the first conductive type. A third doped region of the first conductive type is disposed in the substrate and is adjacent to the second doped region, and a junction is formed between the third doped region and the second doped region. A metal silicide layer is disposed on the substrate. An clearance is formed in the metal silicide layer, and the clearance at least exposes the junction.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 21, 2010
    Applicant: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Shih-Chen Wang, Tsung-Mu Lai
  • Publication number: 20100148238
    Abstract: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 17, 2010
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Shih-Chen Wang, Wen-Hao Ching
  • Publication number: 20100073985
    Abstract: A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.
    Type: Application
    Filed: November 30, 2009
    Publication date: March 25, 2010
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho
  • Publication number: 20090283814
    Abstract: A non-volatile memory cell includes an ion well of a semiconductor substrate; a first half-transistor having a firs select gate, a first diffusion region in the ion well, and a first gate dielectric layer between the first select gate and the ion well; a second half-transistor disposed adjacent to the first half-transistor, wherein the second half-transistor has a second select gate spaced apart from the first select gate, a second diffusion region in the ion well, and a second gate dielectric layer between the second select gate and the ion well. The first and second half-transistors are mirror-symmetrical to each other.
    Type: Application
    Filed: May 19, 2008
    Publication date: November 19, 2009
    Inventors: Hsin-Ming Chen, Shao-Chang Huang, Shih-Chen Wang, Wen-Hao Ching, Chrong-Jung Lin
  • Publication number: 20080296701
    Abstract: A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.
    Type: Application
    Filed: December 14, 2007
    Publication date: December 4, 2008
    Applicant: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho