Patents by Inventor Wen-Hao Ching

Wen-Hao Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160104537
    Abstract: A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.
    Type: Application
    Filed: October 13, 2015
    Publication date: April 14, 2016
    Inventors: Wei-Chen Chang, Wen-Hao Ching, Chih-Hsin Chen, Shih-Chen Wang, Ching-Sung Yang
  • Publication number: 20160035421
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Application
    Filed: October 7, 2015
    Publication date: February 4, 2016
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Patent number: 9153327
    Abstract: A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cell regions. Each of the memory cell regions includes a plurality of memory cells, a programming voltage control generator and an erase voltage control generator. The memory cells receives a programming control voltage through a control end point for programming operation, and the memory cells receives an erase control voltage through an erase end point for erasing operation. The programming voltage control generator provides the programming control voltage to the memory cells, and the erase voltage control generator provides the erase control voltage to the memory cells.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: October 6, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Shih-Chen Wang
  • Patent number: 9099392
    Abstract: The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: August 4, 2015
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Te-Hsun Hsu, Hsin-Ming Chen, Wen-Hao Ching, Wei-Ren Chen
  • Patent number: 9042174
    Abstract: A non-volatile memory cell comprises a coupling device, a first and a second select transistor, and a first and a second floating gate transistor is disclosed. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to the first floating gate transistor and the second select transistor. Moreover, the first select transistor, the first floating gate transistor, and the second select transistor are formed in a second conductivity region. The second floating gate transistor is formed in a third conductivity region, wherein the first conductivity region, the second conductivity region, and the third conductivity region are formed in a fourth conductivity region. The first conductivity region, the second conductivity region, and the third conductivity region are wells, and the fourth conductivity region is a deep well. The third conductivity region surrounds the first conductivity region and the second conductivity region.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: May 26, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Shih-Chen Wang
  • Publication number: 20150092498
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Application
    Filed: May 6, 2014
    Publication date: April 2, 2015
    Applicant: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Patent number: 8958245
    Abstract: The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: February 17, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Te-Hsun Hsu, Wei-Ren Chen, Wen-Hao Ching, Wen-Chuan Chang
  • Publication number: 20140177338
    Abstract: A non-volatile memory cell comprises a coupling device, a first and a second select transistor, and a first and a second floating gate transistor is disclosed. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to the first floating gate transistor and the second select transistor. Moreover, the first select transistor, the first floating gate transistor, and the second select transistor are formed in a second conductivity region. The second floating gate transistor is formed in a third conductivity region, wherein the first conductivity region, the second conductivity region, and the third conductivity region are formed in a fourth conductivity region. The first conductivity region, the second conductivity region, and the third conductivity region are wells, and the fourth conductivity region is a deep well. The third conductivity region surrounds the first conductivity region and the second conductivity region.
    Type: Application
    Filed: February 26, 2014
    Publication date: June 26, 2014
    Applicant: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Shih-Chen Wang
  • Publication number: 20140160859
    Abstract: A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cell regions. Each of the memory cell regions includes a plurality of memory cells, a programming voltage control generator and an erase voltage control generator. The memory cells receives a programming control voltage through a control end point for programming operation, and the memory cells receives an erase control voltage through an erase end point for erasing operation. The programming voltage control generator provides the programming control voltage to the memory cells, and the erase voltage control generator provides the erase control voltage to the memory cells.
    Type: Application
    Filed: February 14, 2014
    Publication date: June 12, 2014
    Applicant: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Shih-Chen Wang
  • Patent number: 8705289
    Abstract: A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: April 22, 2014
    Assignee: eMemory Technology Inc.
    Inventors: Ching-Sung Yang, Wen-Hao Ching, Wei-Ming Ku, Yung-Hsiang Chen, Shih-Chen Wang, Hsin-Ming Chen
  • Patent number: 8658495
    Abstract: The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: February 25, 2014
    Assignee: Ememory Technology Inc.
    Inventors: Te-Hsun Hsu, Hsin-Ming Chen, Wen-Hao Ching, Wei-Ren Chen
  • Patent number: 8625350
    Abstract: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: January 7, 2014
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Shih-Chen Wang, Ching-Sung Yang
  • Patent number: 8592886
    Abstract: An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: November 26, 2013
    Assignee: Ememory Technology Inc.
    Inventors: Te-Hsun Hsu, Hsin-Ming Chen, Ching-Sung Yang, Wen-Hao Ching, Wei-Ren Chen
  • Patent number: 8587036
    Abstract: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: November 19, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Shih-Chen Wang, Wen-Hao Ching
  • Publication number: 20130302977
    Abstract: The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Te-Hsun Hsu, Hsin-Ming Chen, Wen-Hao Ching, Wei-Ren Chen
  • Publication number: 20130234228
    Abstract: An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
    Type: Application
    Filed: August 13, 2012
    Publication date: September 12, 2013
    Applicant: eMemory Technology Inc.
    Inventors: Te-Hsun Hsu, Hsin-Ming Chen, Ching-Sung Yang, Wen-Hao Ching, Wei-Ren Chen
  • Publication number: 20130237048
    Abstract: The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region.
    Type: Application
    Filed: September 4, 2012
    Publication date: September 12, 2013
    Applicant: eMemory Technology Inc.
    Inventors: Te-Hsun Hsu, Hsin-Ming Chen, Wen-Hao Ching, Wei-Ren Chen
  • Publication number: 20130176793
    Abstract: A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Ching-Sung Yang, Wen-Hao Ching, Wei-Ming Ku, Yung-Hsiang Chen, Shih-Chen Wang, Hsin-Ming Chen
  • Patent number: 8456916
    Abstract: An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.
    Type: Grant
    Filed: July 4, 2012
    Date of Patent: June 4, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang
  • Patent number: 8363475
    Abstract: A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: January 29, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang