Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A method is provided. The method includes determining a first bump map indicative of a first set of positions of bumps. The method includes determining, based upon the first bump map, a first plurality of bump densities associated with a plurality of regions of the first bump map. The method includes smoothing the first plurality of bump densities to determine a second plurality of bump densities associated with the plurality of regions of the first bump map. The method includes determining, based upon the second plurality of bump densities, a second bump map indicative of the first set of positions of the bumps and a set of sizes of the bumps.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: A battery pack for an information handling system includes a battery cell configured to provide current to the information handling system, and a battery management unit including an output to the information handling system. The output provides a maximum continuous current (MCC) indication and a peak power (PP) indication. The battery management unit determines an amount of current that the battery cell provides to the information handling system and determines an optimum MCC value that the battery cell can provide to the information handling system. The battery management unit further provides a first value on the PP indication, the first value being greater than the optimum MCC value, sums the amount of current provided to the information handling system that is in excess of the optimum MCC value, determines that the sum is greater than a threshold, and provides a second value on the PP indication, the second value being less than the optimum MCC value.

Abstract: A fan frame body structure includes a first frame body. The first frame body has a first upper end, a first lower end, a first frame wall and a first main flow way. The first main flow way passes through the first frame body and is formed with a first main inlet and a first main outlet respectively at the first upper end and the first lower end. A first subsidiary flow way is disposed in the first frame wall. The first subsidiary flow way is in parallel the first main flow way. The first subsidiary outlet is positioned at the first upper end of the first frame body in flush with and in adjacency to the first main inlet.

Abstract: A fan frame body structure includes a first frame body. The first frame body has a first upper end, a first lower end, a first frame wall and a first main flow way. The first main flow way passes through the first frame body and is formed with a first main inlet and a first main outlet respectively at the first upper end and the first lower end. A first subsidiary flow way is disposed in the first frame wall. The first subsidiary flow way is in parallel the first main flow way. The first subsidiary outlet is positioned at the first upper end of the first frame body in flush with and in adjacency to the first main inlet.

Abstract: A fan frame body structure includes a first frame body. The first frame body has a first upper end, a first lower end, a first frame wall and a first main flow way. The first main flow way passes through the first frame body and is formed with a first main inlet and a first main outlet respectively at the first upper end and the first lower end. A first subsidiary flow way is disposed in the first frame wall. The first subsidiary flow way is in parallel the first main flow way. The first subsidiary outlet is positioned at the first upper end of the first frame body in flush with and in adjacency to the first main inlet.

Abstract: A heat dissipation system with air sensation function includes a chassis, multiple fans, multiple air sensation units and an external control device connected to the fans. The chassis has an installation face for installing the fans thereon. The air sensation units are respectively disposed on the fans for detecting the air state of the corresponding fans to generate an air sensation signal. The external control device serves to receive the air sensation signal transmitted from the air sensation units and compare the data contained in the air sensation signal with preset data so as to control/adjust the rotational speed of the corresponding fans. Accordingly, a uniform airflow flows out of the fans to effectively lower the noise.

Abstract: The present invention relates to a jet structure of a fan rotor, which comprises a fan wheel and at least one connecting channel. The fan wheel has a hub and plural blades disposed on the circumferential side of the hub. The hub has a top portion and a sidewall. Each of the blades has an upper surface and a lower surface which form a high-pressure zone and a low-pressure zone, respectively. The connecting channel is provided with at least one first inlet disposed in the high-pressure zone and at least one first outlet disposed in the low-pressure zone. The first inlet and the first outlet are a first end and a second end of the connecting channel, respectively. By means of the design of the present invention, the effect of noise reduction can be achieved.

Abstract: A fan noise-lowering structure includes a fan frame main body and a connecting pipe. The fan frame main body has a bottom section and a peripheral wall section; the peripheral wall section is externally located around and forwardly extended normal to the bottom section and internally defines an air-stream passage. Further, the peripheral wall section is formed with a first pipe and a second pipe, which are communicable with the air-stream passage defined in the peripheral wall section. The connecting pipe has two ends respectively connected to the first pipe and the second pipe. With the connecting pipe, air at an air outlet of the air-stream passage having higher pressure is guided to generate swirls, which moves toward an air inlet of the air-stream passage to thereby effectively lower the noise produced by the fan in operating.

Abstract: A fan noise-lowering structure includes a fan frame and a connection section. The fan frame has a bottom side and a circumferential wall. The circumferential wall defines an airflow passage. Two ends of the airflow passage respectively have an inlet and an outlet. The connection section is disposed on inner side or outer side of the circumferential wall. The connection section has an internal passage. Two ends of the internal passage respectively have an inlet end and an outlet end. The outlet end is disposed on the inner side of the circumferential wall in connection with the airflow passage near the inlet. The inlet end is disposed on the bottom side in flush with the outlet. The connection section serves to guide the high-pressure air at the outlet to jet to the inlet so as to achieve multiple noise-lowering effects.

Abstract: The present invention relates to a jet structure of a fan rotor, which comprises a fan wheel and at least one connecting channel. The fan wheel has a hub and plural blades disposed on the circumferential side of the hub. The hub has a top portion and a sidewall. Each of the blades has an upper surface and a lower surface which form a high-pressure zone and a low-pressure zone, respectively. The connecting channel is provided with at least one first inlet disposed in the high-pressure zone and at least one first outlet disposed in the low-pressure zone. The first inlet and the first outlet are a first end and a second end of the connecting channel, respectively. By means of the design of the present invention, the effect of noise reduction can be achieved.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

Abstract: A fan noise-lowering structure includes a fan frame and a connection section. The fan frame has a bottom side and a circumferential wall. The circumferential wall defines an airflow passage. Two ends of the airflow passage respectively have an inlet and an outlet. The connection section is disposed on inner side or outer side of the circumferential wall. The connection section has an internal passage. Two ends of the internal passage respectively have an inlet end and an outlet end. The outlet end is disposed on the inner side of the circumferential wall in connection with the airflow passage near the inlet. The inlet end is disposed on the bottom side in flush with the outlet. The connection section serves to guide the high-pressure air at the outlet to jet to the inlet so as to achieve multiple noise-lowering effects.

Abstract: A fan frame body structure includes a first frame body. The first frame body has a first upper end, a first lower end, a first frame wall and a first main flow way. The first main flow way passes through the first frame body and is formed with a first main inlet and a first main outlet respectively at the first upper end and the first lower end. A first subsidiary flow way is disposed in the first frame wall. The first subsidiary flow way is in parallel the first main flow way. The first subsidiary outlet is positioned at the first upper end of the first frame body in flush with and in adjacency to the first main inlet.

Abstract: The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.

Abstract: A fan noise-lowering structure includes a fan frame main body and a connecting pipe. The fan frame main body has a bottom section and a peripheral wall section; the peripheral wall section is externally located around and forwardly extended normal to the bottom section and internally defines an air-stream passage. Further, the peripheral wall section is formed with a first pipe and a second pipe, which are communicable with the air-stream passage defined in the peripheral wall section. The connecting pipe has two ends respectively connected to the first pipe and the second pipe. With the connecting pipe, air at an air outlet of the air-stream passage having higher pressure is guided to generate swirls, which moves toward an air inlet of the air-stream passage to thereby effectively lower the noise produced by the fan in operating.

Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.