Abstract: A fan noise-lowering structure includes a fan frame main body and a connection section. The fan frame main body has a bottom side and a frame peripheral wall. The frame peripheral wall is perpendicularly annularly disposed on the outer rim of the bottom side. The inner rim of the frame peripheral wall defines an airflow passage. Two ends of the airflow passage respectively have an inlet and an outlet. The connection section is disposed in the frame peripheral wall. Two ends of the connection section are connected with the frame peripheral wall. The two ends of the middle passage are an inlet end and an outlet end in communication with the airflow passage. The connection section serves to guide the high-pressure air of the outlet to jet toward the inlet so as to achieve multiple noise-lowering effects.

Abstract: A heat dissipation system with air sensation function includes a chassis, multiple fans, multiple air sensation units and an external control device connected to the fans. The chassis has an installation face for installing the fans thereon. The air sensation units are respectively disposed on the fans for detecting the air state of the corresponding fans to generate an air sensation signal. The external control device serves to receive the air sensation signal transmitted from the air sensation units and compare the data contained in the air sensation signal with preset data so as to control/adjust the rotational speed of the corresponding fans. Accordingly, a uniform airflow flows out of the fans to effectively lower the noise.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.

Abstract: A heat dissipation system with air sensation function includes a chassis, multiple fans, multiple air sensation units and an external control device connected to the fans. The chassis has an installation face for installing the fans thereon. The air sensation units are respectively disposed on the fans for detecting the air state of the corresponding fans to generate an air sensation signal. The external control device serves to receive the air sensation signal transmitted from the air sensation units and compare the data contained in the air sensation signal with preset data so as to control/adjust the rotational speed of the corresponding fans. Accordingly, a uniform airflow flows out of the fans to effectively lower the noise.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: Systems, methods, media, and other such embodiments are described for routing track assignment in a circuit design. One embodiment involves accessing routing data for a circuit design, and a first wire of a plurality of wires in the routing data. A second wire is identified that is related to the first wire as a parent wire along a shared routing direction. A misalignment value is calculated for the first wire and the second wire, and a new routing placement is selected for the first wire based at least in part on the misalignment value. In some embodiments, all wires in various routings of a circuit design are checked for possible misalignment in order to improve slew performance via reduction of unnecessary vias.

Abstract: A fan noise-lowering structure includes a fan frame main body and a connection section. The fan frame main body has a bottom side and a frame peripheral wall. The frame peripheral wall is perpendicularly annularly disposed on the outer rim of the bottom side. The inner rim of the frame peripheral wall defines an airflow passage. Two ends of the airflow passage respectively have an inlet and an outlet. The connection section is disposed in the frame peripheral wall. Two ends of the connection section are connected with the frame peripheral wall. The two ends of the middle passage are an inlet end and an outlet end in communication with the airflow passage. The connection section serves to guide the high-pressure air of the outlet to jet toward the inlet so as to achieve multiple noise-lowering effects.

Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.

Abstract: Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid lines into the grid structure such that each partition boundary is aligned with a grid line. The method may further include removing redundant grid lines from the non-uniform grid graph resulting from inserting the additional grid lines, the result of which is the partition-aware grid graph. The method further includes using the partition-aware grid graph to route the integrated circuit design.

Abstract: Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing path in the net is then rerouted using the routing guide, thereby producing an enhanced routing topology that reduces issues in detailed routing caused by the routing constraint violation.

Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.

Abstract: Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.

Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.

Abstract: Aspects of the present disclosure address improved systems and methods for local cluster refinement during clock tree synthesis for integrated circuit designs. In accordance with some embodiments, the methods for local cluster refinement may include pin move refinement and local reclustering. With pin move refinement, pins are moved from clusters that fail to satisfy design rule constraints to nearby clusters that satisfy design rule constraints. With local reclustering, groups of neighboring clusters that fail or nearly fail to satisfy design rule constraints are dissolved and corresponding pins are regrouped to form new clusters that satisfy design rule constraints.

Abstract: Various embodiments provide for clustering pins of a circuit design for connection to a power-ground network (PG) of the circuit design using a nearest neighbor graph. Pin clustering, according to some embodiments, can minimize wirelength, minimize a number of vias, satisfy constraints relating to a pin count (e.g., maximum number of pins per power-ground access point), and satisfy constraints relating to a bounding box size.

Abstract: Methods and systems of optimization of and Integrated Circuit (IC) design disclosed herein result in a power efficient clustering of circuit devices. The methods may depart from the conventional geometric clustering using a nearest neighbor approach when wiring flops to local clock buffers. To reduce the number of clock-gaters, the methods in one embodiment use a grouping of flops wired to a common clock-gater to form nodes, which are then wired to the local clock buffers based on a load-balancing process. In another embodiment, the methods use a local cleanup process to rewire the nodes between neighboring clock buffers to further reduce the amount of clock-gaters.

Abstract: The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.

Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.

Abstract: Disclosed herein are systems and methods to construct a symmetric clock-distribution H-tree in upper layers of an integrated circuit (IC), which may have complicated routing and/or placement blockages. The systems and methods disclosed herein may implement concomitant bottom-up wiring and top-down rewiring to achieve a clock-distribution tree symmetrically balanced across all of the hierarchical levels while respecting the complicated routing and/or placement blockages. Such symmetrically balanced clock-tree ensures that a clock-signal reaches all of the clock-sinks simultaneously or near simultaneously thereby minimizing clock-skew across the clock-sinks. The minimal skew symmetric clock-distribution H-tree may therefore be used for higher performance and high speed ICs.