Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

Abstract: A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.

Abstract: A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.

Abstract: A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.

Abstract: By using a photosensitive material coating or laminating on the substrate, an opening well structure with plurality of openings and pillars is formed by photolithography or mechanical processing to have patterns corresponding to the active sensor areas of the chip die so as to provide improved support on the substrate for the cover glass. The overall package structure is then reinforced without the risk of cracking the substrate.

Abstract: A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.

Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.

Abstract: A semiconductor package including a first semiconductor chip, a plurality of first conductors, a first conductive pattern electrically connected to the first conductors, a second semiconductor chip disposed on the first semiconductor chip, and an encapsulant on the first conductive pattern and laterally encapsulating the second semiconductor chip. The first semiconductor chip electrically connected to the first conductors includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending form the first back surface towards the first active surface. The second semiconductor chip including a second active surface facing towards the first back surface electrically connects the first semiconductor chip through the first conductors in the through holes and the first conductive pattern on the first back surface. A manufacturing method of a semiconductor package is also provided.

Abstract: A manufacturing method for a metallic housing of an electronic device is provided. The method includes providing a die-casting mold including a male die and a female die; positioning an outer frame in a cavity of the female die, the outer frame including a plurality of latching portions protruding from an inner surface inwardly and a plurality of latching grooves, each latching portion including at least one receiving groove; assembling the male die to the female die; casting pressured molten metal-alloy into the cavity to form an inner structural member embedded in the outer frame, the inner structural member including a plurality of engaging portions respectively embedded in the plurality of receiving grooves, and a plurality of matching portions respectively embedded in the plurality of latching grooves; dissembling the male die from the female die; and removing the outer frame and the inner structural member from the female die.

Abstract: A manufacturing method for a metallic housing of an electronic device is provided. The method includes providing a die-casting mold, including a male die and a female die engaging with the male die, the male die defining a pouring gate therein, and the female die defining a cavity therein corresponding to the pouring gate; positioning a metallic outer case in the cavity of the female die as an insert; assembling the male die to the female die to cover the cavity, thereby communicating the pouring gate with the cavity; casting pressured molten metal-alloy into the cavity via the pouring gate to form an inner structural member embedded in an inner side of the outer case; dissembling the male die from the female die to expose the cavity, and removing the outer case and the inner structural member from the female die.

Abstract: A metallic article can include a cast metallic body and at least one metallic element. The cast metallic body defines at least one first space. The least one metallic element is received in the cast metallic body and seamless with the cast metallic body. The at least one metallic element is exposed from the at least one first space. A heat conductivity of the cast metallic body is lower than that of the at least one metallic element. The present disclosure further provides a method for manufacturing metallic article.

Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.

Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.

Abstract: A metallic article can include a cast metallic body and at least one metallic element. The cast metallic body defines at least one first space. The least one metallic element is received in the cast metallic body and seamless with the cast metallic body. The at least one metallic element is exposed from the at least one first space. A heat conductivity of the cast metallic body is lower than that of the at least one metallic element. The present disclosure further provides a method for manufacturing metallic article.

Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.

Abstract: A folding stool includes a pair of table surface sections, a pair of leg sections, and a pivot member. The pair of table surface sections is connected to each other by the pivot member, and the pair of leg sections supports the pair of table surface sections. Each leg section includes a bottom and a top, and the top resists against the table surface section. The folding stool is made of aluminum and magnesium alloy, further includes a plurality of first connecting members and a plurality of second connecting members. Each table surface section includes a first connecting hole and a second connecting hole, and each leg section includes a third connecting hole and a fourth connecting hole. The first connecting member is connected between first connecting hole and the third connecting hole, and the second connecting member is connected between second connecting hole and the fourth connecting hole.

Abstract: A manufacturing method for a metallic housing of an electronic device is provided. The method includes providing a die-casting mold including a male die and a female die; positioning an outer frame in a cavity of the female die, the outer frame including a plurality of latching portions protruding from an inner surface inwardly and a plurality of latching grooves, each latching portion including at least one receiving groove; assembling the male die to the female die; casting pressured molten metal-alloy into the cavity to form an inner structural member embedded in the outer frame, the inner structural member including a plurality of engaging portions respectively embedded in the plurality of receiving grooves, and a plurality of matching portions respectively embedded in the plurality of latching grooves; dissembling the male die from the female die; and removing the outer frame and the inner structural member from the female die.

Abstract: A manufacturing method for a metallic housing of an electronic device is provided. The method includes providing a die-casting mold, including a male die and a female die engaging with the male die, the male die defining a pouring gate therein, and the female die defining a cavity therein corresponding to the pouring gate; positioning a metallic outer case in the cavity of the female die as an insert; assembling the male die to the female die to cover the cavity, thereby communicating the pouring gate with the cavity; casting pressured molten metal-alloy into the cavity via the pouring gate to form an inner structural member embedded in an inner side of the outer case; dissembling the male die from the female die to expose the cavity, and removing the outer case and the inner structural member from the female die.

Abstract: A resistive memory apparatus is provided. The resistive memory apparatus includes a plurality of memory cell pairs, and each of the memory cell pairs includes an active area, first and second word lines, a source line, first and second resistors and first and second bit lines. The active area is formed on a substrate, and the first and second word lines are formed on the substrate, and intersected with the active area. The source line is formed on the substrate and coupled to the active area. The first and second resistors are disposed on the substrate, and respectively coupled to the active area. The first and second bit lines are formed on the first and second resistors and coupled to the first and second resistors. The first and second bit lines are extended along a first direction which is substantially parallel to the first and second word lines.

Abstract: A metallic housing of an electronic device, includes a metallic outer frame and an inner structural member. The metallic outer frame comprises a plurality of latching portions protruding, and a plurality of latching grooves. The inner structural member is made from metal-alloy and embedded in the outer frame by die-casting. The inner structural member comprises a peripheral sidewall, a plurality of engaging portions, and a plurality of matching portions. The plurality of engaging portions and the plurality of matching portions protrude from the peripheral sidewall outwardly. Each latching portion comprises at least two parallel latching ribs, and forms a receiving groove between two adjacent latching ribs. The plurality of engaging portions is respectively embedded in the plurality of receiving grooves, and the plurality of matching portions is respectively embedded in the plurality of latching grooves. The present disclosure further provides a manufacturing method for the metallic housing.