Patents by Inventor Wen Hsiung Chang

Wen Hsiung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200166155
    Abstract: A micro fluid actuator includes an orifice layer, a flow channel layer, a substrate, a chamber layer, a vibration layer, a lower electrode layer, a piezoelectric actuation layer and an upper electrode layer, which are stacked sequentially. An outflow aperture, a plurality of first inflow apertures and a second inflow aperture are formed in the substrate by an etching process. A storage chamber is formed in the chamber layer by the etching process. An outflow opening and an inflow opening are formed in the orifice layer by the etching process. An outflow channel, an inflow channel and a plurality of columnar structures are formed in the flow channel layer by a lithography process. By providing driving power which have different phases to the upper electrode layer and the lower electrode layer, the vibration layer is driven to displace in a reciprocating manner, so as to achieve fluid transportation.
    Type: Application
    Filed: October 23, 2019
    Publication date: May 28, 2020
    Applicant: Microjet Technology Co., Ltd.
    Inventors: Hao-Jan Mou, Rong-Ho Yu, Cheng-Ming Chang, Hsien-Chung Tai, Wen-Hsiung Liao, Chi-Feng Huang, Yung-Lung Han, Hsuan-Kai Chen
  • Publication number: 20200140264
    Abstract: A manufacturing method of micro channel structure is disclosed and includes steps of: providing a substrate; depositing and etching to form a first insulation layer; depositing and etching to form a supporting layer; depositing and etching to form a valve layer; depositing and etching to form a second insulation layer; depositing and etching to form a vibration layer, a lower electrode layer and a piezoelectric actuating layer; providing a photoresist layer and depositing and etching to form a plurality of bonding pads; depositing and etching to from a mask layer; etching to form a first chamber; and etching to form a second chamber.
    Type: Application
    Filed: October 23, 2019
    Publication date: May 7, 2020
    Applicant: Microjet Technology Co., Ltd.
    Inventors: Hao-Jan Mou, Rong-Ho Yu, Cheng-Ming Chang, Hsien-Chung Tai, Wen-Hsiung Liao, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai
  • Publication number: 20200139368
    Abstract: A micro channel structure includes a substrate, a supporting layer, a valve layer, a second insulation layer, a vibration layer and a bonding-pad layer. A flow channel is formed on the substrate. A conductive part and a movable part are formed on the supporting layer and the valve layer, respectively. A first chamber is formed at the interior of a base part and communicates to the hollow aperture. A supporting part is formed on the second insulation layer. A second chamber is formed at the interior of the supporting layer and communicates to the first chamber through the hollow aperture. A suspension part is formed on the vibration layer. By providing driving power sources having different phases to the bonding-pad layer, the suspension part moves upwardly and downwardly, and a relative displacement is generated between the movable part and the conductive part, to achieve fluid transportation.
    Type: Application
    Filed: October 23, 2019
    Publication date: May 7, 2020
    Applicant: Microjet Technology Co., Ltd.
    Inventors: Hao-Jan Mou, Rong-Ho Yu, Cheng-Ming Chang, Hsien-Chung Tai, Wen-Hsiung Liao, Chi-Feng Huang, Yung-Lung Han, Chun-Yi Kuo
  • Publication number: 20200091126
    Abstract: A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.
    Type: Application
    Filed: November 19, 2019
    Publication date: March 19, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Wen-Hsiung Chang
  • Publication number: 20200088185
    Abstract: A MEMS pump includes a first substrate, a first oxide layer, a second substrate, a second oxide layer, a third substrate and a piezoelectric element sequentially stacked to form the entire structure of the MEMS pump. The first substrate has a first thickness and at least one inlet aperture. The first oxide layer has at least one fluid inlet channel and a convergence chamber, wherein the fluid inlet channel communicates with the convergence chamber and the inlet aperture. The second substrate has a second thickness and a through hole, and the through hole is misaligned with the inlet aperture and communicates with the convergence chamber. The second oxide layer has a first chamber with a concave central portion. The third substrate has a third thickness and a plurality of gas flow channels, wherein the gas flow channels are misaligned with the through hole.
    Type: Application
    Filed: September 13, 2019
    Publication date: March 19, 2020
    Applicant: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Rong-Ho Yu, Cheng-Ming Chang, Hsien-Chung Tai, Wen-Hsiung Liao, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai
  • Patent number: 10424526
    Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 24, 2019
    Assignee: Powertech Technology Inc.
    Inventors: Chi-An Wang, Hung-Hsin Hsu, Wen-Hsiung Chang
  • Publication number: 20190144841
    Abstract: Disclosed herein are recombinant polynucleotide sequences, vectors, host cells and methods for producing astaxanthin. The recombinant polynucleotide sequence is designed to provide a higher level of astaxanthin precursors via a shorter metabolic pathway, and thereby attains higher level of end products (e.g., astaxanthin) with desired stereoisomeric form and/or esterified form.
    Type: Application
    Filed: November 26, 2018
    Publication date: May 16, 2019
    Inventors: Jui-Jen CHANG, Caroline THIA, Hao-Yeh LIN, Yu-Ju LIN, Chieh-Chen HUANG, Wen-Hsiung LI
  • Publication number: 20190096866
    Abstract: A semiconductor package including a first semiconductor chip, a plurality of first conductors, a first conductive pattern electrically connected to the first conductors, a second semiconductor chip disposed on the first semiconductor chip, and an encapsulant on the first conductive pattern and laterally encapsulating the second semiconductor chip. The first semiconductor chip electrically connected to the first conductors includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending form the first back surface towards the first active surface. The second semiconductor chip including a second active surface facing towards the first back surface electrically connects the first semiconductor chip through the first conductors in the through holes and the first conductive pattern on the first back surface. A manufacturing method of a semiconductor package is also provided.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Ching-Ming Hsu, Wen-Hsiung Chang, Po-Wei Yeh, Yun-Hsin Yeh
  • Patent number: 10124405
    Abstract: A manufacturing method for a metallic housing of an electronic device is provided. The method includes providing a die-casting mold including a male die and a female die; positioning an outer frame in a cavity of the female die, the outer frame including a plurality of latching portions protruding from an inner surface inwardly and a plurality of latching grooves, each latching portion including at least one receiving groove; assembling the male die to the female die; casting pressured molten metal-alloy into the cavity to form an inner structural member embedded in the outer frame, the inner structural member including a plurality of engaging portions respectively embedded in the plurality of receiving grooves, and a plurality of matching portions respectively embedded in the plurality of latching grooves; dissembling the male die from the female die; and removing the outer frame and the inner structural member from the female die.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: November 13, 2018
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Cai-Hua Wang, Yue-Jian Li, Chen-Shen Lin, Wen-Hsiung Chang, Chun-Jung Chang
  • Patent number: 10040120
    Abstract: A manufacturing method for a metallic housing of an electronic device is provided. The method includes providing a die-casting mold, including a male die and a female die engaging with the male die, the male die defining a pouring gate therein, and the female die defining a cavity therein corresponding to the pouring gate; positioning a metallic outer case in the cavity of the female die as an insert; assembling the male die to the female die to cover the cavity, thereby communicating the pouring gate with the cavity; casting pressured molten metal-alloy into the cavity via the pouring gate to form an inner structural member embedded in an inner side of the outer case; dissembling the male die from the female die to expose the cavity, and removing the outer case and the inner structural member from the female die.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: August 7, 2018
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Cai-Hua Wang, Yue-Jian Li, Chen-Shen Lin, Wen-Hsiung Chang, Chun-Jung Chang
  • Publication number: 20180141114
    Abstract: A metallic article can include a cast metallic body and at least one metallic element. The cast metallic body defines at least one first space. The least one metallic element is received in the cast metallic body and seamless with the cast metallic body. The at least one metallic element is exposed from the at least one first space. A heat conductivity of the cast metallic body is lower than that of the at least one metallic element. The present disclosure further provides a method for manufacturing metallic article.
    Type: Application
    Filed: January 11, 2018
    Publication date: May 24, 2018
    Inventors: JUN-JUN YANG, CAI-HUA WANG, YUE-JIAN LI, CHEN-SHEN LIN, WEN-HSIUNG CHANG, CHUN-JUNG CHANG
  • Patent number: 9972554
    Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 15, 2018
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Li-Chih Fang, Chia-Chang Chang, Hung-Hsin Hsu, Wen-Hsiung Chang, Kee-Wei Chung, Chia-Wen Lien
  • Publication number: 20180114734
    Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 26, 2018
    Applicant: Powertech Technology Inc.
    Inventors: Chi-An Wang, Hung-Hsin Hsu, Wen-Hsiung Chang
  • Patent number: 9901979
    Abstract: A metallic article can include a cast metallic body and at least one metallic element. The cast metallic body defines at least one first space. The least one metallic element is received in the cast metallic body and seamless with the cast metallic body. The at least one metallic element is exposed from the at least one first space. A heat conductivity of the cast metallic body is lower than that of the at least one metallic element. The present disclosure further provides a method for manufacturing metallic article.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 27, 2018
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jun-Jun Yang, Cai-Hua Wang, Yue-Jian Li, Chen-Shen Lin, Wen-Hsiung Chang, Chun-Jung Chang
  • Publication number: 20170256471
    Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.
    Type: Application
    Filed: February 15, 2017
    Publication date: September 7, 2017
    Inventors: Li-Chih Fang, Chia-Chang Chang, Hung-Hsin Hsu, Wen-Hsiung Chang, Kee-Wei Chung, Chia-Wen Lien
  • Publication number: 20160309903
    Abstract: A folding stool includes a pair of table surface sections, a pair of leg sections, and a pivot member. The pair of table surface sections is connected to each other by the pivot member, and the pair of leg sections supports the pair of table surface sections. Each leg section includes a bottom and a top, and the top resists against the table surface section. The folding stool is made of aluminum and magnesium alloy, further includes a plurality of first connecting members and a plurality of second connecting members. Each table surface section includes a first connecting hole and a second connecting hole, and each leg section includes a third connecting hole and a fourth connecting hole. The first connecting member is connected between first connecting hole and the third connecting hole, and the second connecting member is connected between second connecting hole and the fourth connecting hole.
    Type: Application
    Filed: May 19, 2015
    Publication date: October 27, 2016
    Inventors: BO HUANG, JUN-XIAO LIU, HONG-ZHAO QI, CAI-HUA WANG, YUE-JIAN LI, CHEN-SHEN LIN, WEN-HSIUNG CHANG, CHUN-JUNG CHANG
  • Publication number: 20160263650
    Abstract: A manufacturing method for a metallic housing of an electronic device is provided. The method includes providing a die-casting mold including a male die and a female die; positioning an outer frame in a cavity of the female die, the outer frame including a plurality of latching portions protruding from an inner surface inwardly and a plurality of latching grooves, each latching portion including at least one receiving groove; assembling the male die to the female die; casting pressured molten metal-alloy into the cavity to form an inner structural member embedded in the outer frame, the inner structural member including a plurality of engaging portions respectively embedded in the plurality of receiving grooves, and a plurality of matching portions respectively embedded in the plurality of latching grooves; dissembling the male die from the female die; and removing the outer frame and the inner structural member from the female die.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Inventors: CAI-HUA WANG, YUE-JIAN LI, CHEN-SHEN LIN, WEN-HSIUNG CHANG, CHUN-JUNG CHANG
  • Publication number: 20160207104
    Abstract: A manufacturing method for a metallic housing of an electronic device is provided. The method includes providing a die-casting mold, including a male die and a female die engaging with the male die, the male die defining a pouring gate therein, and the female die defining a cavity therein corresponding to the pouring gate; positioning a metallic outer case in the cavity of the female die as an insert; assembling the male die to the female die to cover the cavity, thereby communicating the pouring gate with the cavity; casting pressured molten metal-alloy into the cavity via the pouring gate to form an inner structural member embedded in an inner side of the outer case; dissembling the male die from the female die to expose the cavity, and removing the outer case and the inner structural member from the female die.
    Type: Application
    Filed: March 29, 2016
    Publication date: July 21, 2016
    Inventors: CAI-HUA WANG, YUE-JIAN LI, CHEN-SHEN LIN, WEN-HSIUNG CHANG, CHUN-JUNG CHANG
  • Patent number: 9373391
    Abstract: A resistive memory apparatus is provided. The resistive memory apparatus includes a plurality of memory cell pairs, and each of the memory cell pairs includes an active area, first and second word lines, a source line, first and second resistors and first and second bit lines. The active area is formed on a substrate, and the first and second word lines are formed on the substrate, and intersected with the active area. The source line is formed on the substrate and coupled to the active area. The first and second resistors are disposed on the substrate, and respectively coupled to the active area. The first and second bit lines are formed on the first and second resistors and coupled to the first and second resistors. The first and second bit lines are extended along a first direction which is substantially parallel to the first and second word lines.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: June 21, 2016
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Wen-Hsiung Chang, Chien-Min Wu
  • Patent number: 9370823
    Abstract: A metallic housing of an electronic device, includes a metallic outer frame and an inner structural member. The metallic outer frame comprises a plurality of latching portions protruding, and a plurality of latching grooves. The inner structural member is made from metal-alloy and embedded in the outer frame by die-casting. The inner structural member comprises a peripheral sidewall, a plurality of engaging portions, and a plurality of matching portions. The plurality of engaging portions and the plurality of matching portions protrude from the peripheral sidewall outwardly. Each latching portion comprises at least two parallel latching ribs, and forms a receiving groove between two adjacent latching ribs. The plurality of engaging portions is respectively embedded in the plurality of receiving grooves, and the plurality of matching portions is respectively embedded in the plurality of latching grooves. The present disclosure further provides a manufacturing method for the metallic housing.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: June 21, 2016
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Cai-Hua Wang, Yue-Jian Li, Chen-Shen Lin, Wen-Hsiung Chang, Chun-Jung Chang