Patents by Inventor Wen-Huei Guo
Wen-Huei Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160155739Abstract: An embodiment is a method including forming a first fin on a substrate, the first fin having a first longitudinal axis, forming a first trench having a first width in the first fin, the first trench dividing the first fin into at least two fin portions, forming a first gate structure and first source/drain regions over one of the at least two fin portions of the first fin, and forming a second gate structure and second source/drain regions over another of the at least two fin portions of the first fin.Type: ApplicationFiled: December 1, 2014Publication date: June 2, 2016Inventors: Kuo-Chiang Ting, Jyh-Huei Chen, Wen-Huei Guo, Cheng-Han Wu, Yu-Wei Lee
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Publication number: 20150348967Abstract: Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.Type: ApplicationFiled: August 7, 2015Publication date: December 3, 2015Inventors: Tung Ying Lee, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang
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Publication number: 20150270153Abstract: An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.Type: ApplicationFiled: June 8, 2015Publication date: September 24, 2015Inventors: I-Ming Chang, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang, Clement Hsingjen Wann, Tung Ying Lee, Cheng-Long Chen, Jui-Chien Huang
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Publication number: 20150228743Abstract: An apparatus includes a semiconductor substrate having a plurality of fins, wherein the plurality of fins includes a first group of fins and a second group of fins. The apparatus further includes a high fin density area on the semiconductor substrate including a first dielectric between the first group of fins in the high fin density area, said first dielectric having a first dopant concentration. The apparatus further includes a low fin density area on the semiconductor substrate including a second dielectric between the second group of fins in the low fin density area, said second dielectric having a second dopant concentration. The first dielectric and the second dielectric are a same material as deposited and the first dopant concentration and the second dopant concentration are different.Type: ApplicationFiled: April 22, 2015Publication date: August 13, 2015Inventors: Clement Hsingjen WANN, Ling-Yen YEH, Chi-Yuan SHIH, Yuan-Fu SHAO, Wen-Huei GUO, Tung Ying LEE
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Patent number: 9105744Abstract: Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.Type: GrantFiled: March 1, 2012Date of Patent: August 11, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang
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Patent number: 9054188Abstract: An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.Type: GrantFiled: February 24, 2012Date of Patent: June 9, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Ming Chang, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang, Clement Hsingjen Wann, Tung Ying Lee, Cheng-Long Chen, Jui-Chien Huang
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Patent number: 9041158Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited.Type: GrantFiled: February 23, 2012Date of Patent: May 26, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wen-Huei Guo, Tung Ying Lee
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Patent number: 8754486Abstract: A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode.Type: GrantFiled: June 14, 2013Date of Patent: June 17, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang
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Publication number: 20130277744Abstract: A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode.Type: ApplicationFiled: June 14, 2013Publication date: October 24, 2013Inventors: Tung Ying Lee, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang
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Patent number: 8558278Abstract: A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.Type: GrantFiled: September 4, 2007Date of Patent: October 15, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Wen-Huei Guo, Mong Song Liang
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Patent number: 8551841Abstract: A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode.Type: GrantFiled: January 6, 2012Date of Patent: October 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang
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Publication number: 20130221491Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited.Type: ApplicationFiled: February 23, 2012Publication date: August 29, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wen-Huei Guo, Tung Ying Lee
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Publication number: 20130224952Abstract: An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.Type: ApplicationFiled: February 24, 2012Publication date: August 29, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Ming Chang, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang, Clement Hsingjen Wann, Tung Ying Lee, Cheng-Long Chen, Jui-Chien Huang
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Publication number: 20130175578Abstract: A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode.Type: ApplicationFiled: January 6, 2012Publication date: July 11, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang
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Patent number: 7678636Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.Type: GrantFiled: September 13, 2006Date of Patent: March 16, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Mong-Song Liang, Kong-Beng Thei, Jung-Hui Kao, Chung Long Cheng, Sheng-Chen Chung, Wen-Huei Guo
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Patent number: 7632729Abstract: A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.Type: GrantFiled: September 27, 2006Date of Patent: December 15, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Chung-Long Cheng, Sheng-Chen Chung, Wen-Huei Guo, Jung-Hui Kao, Ryan Chia-Jen Chen, Mong-Song Liang
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Publication number: 20080169484Abstract: A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.Type: ApplicationFiled: September 4, 2007Publication date: July 17, 2008Inventors: Harry Chuang, Kong-Beng Thei, Wen-Huei Guo, Mong Song Liang
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Publication number: 20080076215Abstract: A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.Type: ApplicationFiled: September 27, 2006Publication date: March 27, 2008Inventors: Harry Chuang, Kong-Beng Thei, Chung-Long Cheng, Sheng-Chen Chung, Wen-Huei Guo, Jung-Hui Kao, Ryan Chia-Jen Chen, Mong-Song Liang
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Publication number: 20080003734Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.Type: ApplicationFiled: September 13, 2006Publication date: January 3, 2008Inventors: Harry Chuang, Mong-Song Liang, Kong-Beng Thei, Jung-Hui Kao, Chung Long Cheng, Sheng-Chen Chung, Wen-Huei Guo